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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Made an attempt to wire in an [unclocked] AY, in an endeavour to get to keyboard reading.
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@ -253,20 +253,40 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
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public:
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void set_value(int port, uint8_t value) {
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switch(port) {
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case 0: printf("PSG data: %d\n", value); break;
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case 0:
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ay_->set_data_input(value);
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break;
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case 1: printf("Vsync, etc: %02x\n", value); break;
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case 2: printf("Key row, etc: %02x\n", value); break;
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case 2:
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// TODO: set key row: (value & 15)
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// TODO: set casette motor control: ((value >> 4) & 1)
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// TODO: set casette output: ((value >> 5) & 1)
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ay_->set_control_lines(
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(GI::AY38910::ControlLines)(
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((value & 0x80) ? GI::AY38910::BCDIR : 0) |
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((value & 0x40) ? GI::AY38910::BC1 : 0)
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));
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break;
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}
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}
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uint8_t get_value(int port) {
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switch(port) {
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case 0: printf("PSG data\n"); break;
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case 0:
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return ay_->get_data_output();
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break;
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case 1: printf("[In] Vsync, etc\n"); break;
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case 2: printf("[In] Key row, etc\n"); break;
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}
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return 0xff;
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}
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void set_ay(std::shared_ptr<GI::AY38910> ay) {
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ay_ = ay;
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}
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private:
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std::shared_ptr<GI::AY38910> ay_;
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};
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class ConcreteMachine:
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@ -276,7 +296,8 @@ class ConcreteMachine:
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ConcreteMachine() :
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crtc_counter_(HalfCycles(4)), // This starts the CRTC exactly out of phase with the memory accesses
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crtc_(crtc_bus_handler_),
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crtc_bus_handler_(ram_) {
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crtc_bus_handler_(ram_),
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i8255_(i8255_port_handler_) {
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// primary clock is 4Mhz
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set_clock_rate(4000000);
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}
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@ -368,14 +389,19 @@ class ConcreteMachine:
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return HalfCycles(0);
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}
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void flush() {}
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void flush() {
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// i8255_port_handler_.flush();
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}
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void setup_output(float aspect_ratio) {
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crtc_bus_handler_.setup_output(aspect_ratio);
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ay_.reset(new GI::AY38910);
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i8255_port_handler_.set_ay(ay_);
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}
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void close_output() {
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crtc_bus_handler_.close_output();
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ay_.reset();
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}
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std::shared_ptr<Outputs::CRT::CRT> get_crt() {
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@ -383,7 +409,7 @@ class ConcreteMachine:
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}
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std::shared_ptr<Outputs::Speaker> get_speaker() {
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return nullptr;
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return ay_;
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}
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void run_for(const Cycles cycles) {
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@ -416,11 +442,13 @@ class ConcreteMachine:
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CRTCBusHandler crtc_bus_handler_;
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Motorola::CRTC::CRTC6845<CRTCBusHandler> crtc_;
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std::shared_ptr<GI::AY38910> ay_;
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i8255PortHandler i8255_port_handler_;
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Intel::i8255::i8255<i8255PortHandler> i8255_;
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HalfCycles clock_offset_;
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HalfCycles crtc_counter_;
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HalfCycles half_cycles_since_ay_update_;
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uint8_t ram_[65536];
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std::vector<uint8_t> os_, basic_;
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