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https://github.com/TomHarte/CLK.git
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After much extra logging, corrects destination bank for MVN and MVP.
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1538a02e18
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@ -177,6 +177,7 @@ class ConcreteMachine:
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forceinline Cycles perform_bus_operation(const CPU::WDC65816::BusOperation operation, const uint32_t address, uint8_t *const value) {
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const auto ®ion = MemoryMapRegion(memory_, address);
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static bool log = false;
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static uint64_t total = 0;
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bool is_1Mhz = (region.flags & MemoryMap::Region::Is1Mhz) || !(speed_register_ & 0x80) || (speed_register_ & motor_flags_);
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if(region.flags & MemoryMap::Region::IsIO) {
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@ -554,7 +555,11 @@ class ConcreteMachine:
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} else {
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switch(address_suffix) {
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default:
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printf("Internal card-area access: %04x\n", address_suffix);
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// Temporary: log _potential_ mistakes.
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if(address_suffix < 0xc100) {
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printf("Internal card-area access: %04x\n", address_suffix);
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log |= operation == CPU::WDC65816::BusOperation::ReadOpcode;
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}
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if(is_read) {
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*value = rom_[rom_.size() - 65536 + address_suffix];
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}
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@ -620,10 +625,16 @@ class ConcreteMachine:
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// operation == CPU::WDC65816::BusOperation::ReadOpcode ? " [*]" : "");
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// }
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// log |= (address >= 0xff9b00) && (address < 0xff9b32);
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if(log) {
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// log |= (operation == CPU::WDC65816::BusOperation::ReadOpcode) && (address < 0x100);
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// log |= total >= 77750000;
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// log |= (address == 0x1f6) && (total >= 60000000);
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// log |= (address == 0x48) && (*value == 0x02);
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// log |= (operation == CPU::WDC65816::BusOperation::ReadOpcode) && (address >= 0x800) && (address < 0x900);
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// log &= !((operation == CPU::WDC65816::BusOperation::ReadOpcode) && (address == 0x0002));
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if(log || address == 0x48 || address == 0x49) {
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printf("%06x %s %02x", address, isReadOperation(operation) ? "->" : "<-", *value);
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if(operation == CPU::WDC65816::BusOperation::ReadOpcode) {
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printf(" a:%04x x:%04x y:%04x s:%04x e:%d p:%02x db:%02x pb:%02x d:%04x\n",
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printf(" a:%04x x:%04x y:%04x s:%04x e:%d p:%02x db:%02x pb:%02x d:%04x [tot:%llu]\n",
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m65816_.get_value_of_register(CPU::WDC65816::Register::A),
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m65816_.get_value_of_register(CPU::WDC65816::Register::X),
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m65816_.get_value_of_register(CPU::WDC65816::Register::Y),
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@ -632,8 +643,8 @@ class ConcreteMachine:
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m65816_.get_value_of_register(CPU::WDC65816::Register::Flags),
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m65816_.get_value_of_register(CPU::WDC65816::Register::DataBank),
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m65816_.get_value_of_register(CPU::WDC65816::Register::ProgramBank),
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m65816_.get_value_of_register(CPU::WDC65816::Register::Direct
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)
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m65816_.get_value_of_register(CPU::WDC65816::Register::Direct),
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total
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);
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} else printf("\n");
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}
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@ -651,8 +662,8 @@ class ConcreteMachine:
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} else {
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// Clues as to 'fast' refresh timing:
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//
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// (i) "The time required for the refresh cycles reduces the effective processor speed
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// for programs in RAM by about 8 percent.";
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// (i) "The time required for the refresh cycles reduces the effective
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// processor speed for programs in RAM by about 8 percent.";
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// (ii) "These cycles occur approximately every 3.5 microseconds"
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//
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// 3.5µs @ 14,318,180Hz => one every 50.11 cycles. Safe to assume every 10th fast cycle
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@ -663,6 +674,7 @@ class ConcreteMachine:
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const int refresh = (fast_access_phase_ / 45) * bool(region.write) * 5;
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duration = Cycles(5 + phase_adjust + refresh);
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}
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// TODO: lookup tables to avoid the above? LCM of the two phases is 22,800 so probably 912+50 bytes plus two counters.
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fast_access_phase_ = (fast_access_phase_ + duration.as<int>()) % 50;
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slow_access_phase_ = (slow_access_phase_ + duration.as<int>()) % 912;
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@ -679,6 +691,7 @@ class ConcreteMachine:
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video_ += duration;
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iwm_ += duration;
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cycles_since_audio_update_ += duration;
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total += decltype(total)(duration.as_integral());
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// Ensure no more than a single line is enqueued for just-in-time video purposes.
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// TODO: as implemented, check_flush_threshold doesn't actually work. Can it be made to without forcing cost to non-users, or is it a bad idea?
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@ -145,11 +145,11 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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break;
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case CycleFetchBlockY:
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perform_bus(((instruction_buffer_.value & 0xff00) << 8) | registers_.y.full, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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perform_bus(((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
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break;
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case CycleStoreBlockY:
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write(((instruction_buffer_.value & 0xff00) << 8) | registers_.y.full, data_buffer_.any_byte());
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write(((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full, data_buffer_.any_byte());
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break;
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#undef increment_data_address
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