From ced644b1038981cc8dec416ea2290939121100a2 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Wed, 11 Jan 2017 22:03:01 -0500 Subject: [PATCH] It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock. --- Components/AY38910/AY38910.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Components/AY38910/AY38910.cpp b/Components/AY38910/AY38910.cpp index 93534d872..2ac9d3177 100644 --- a/Components/AY38910/AY38910.cpp +++ b/Components/AY38910/AY38910.cpp @@ -84,7 +84,7 @@ void AY38910::set_clock_rate(double clock_rate) void AY38910::get_samples(unsigned int number_of_samples, int16_t *target) { int c = 0; - while((master_divider_&15) && c < number_of_samples) + while((master_divider_&7) && c < number_of_samples) { target[c] = output_volume_; master_divider_++; @@ -131,7 +131,7 @@ void AY38910::get_samples(unsigned int number_of_samples, int16_t *target) evaluate_output_volume(); - for(int ic = 0; ic < 16 && c < number_of_samples; ic++) + for(int ic = 0; ic < 8 && c < number_of_samples; ic++) { target[c] = output_volume_; c++; @@ -139,7 +139,7 @@ void AY38910::get_samples(unsigned int number_of_samples, int16_t *target) } } - master_divider_ &= 15; + master_divider_ &= 7; } void AY38910::evaluate_output_volume()