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https://github.com/TomHarte/CLK.git
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Pull PagingType::Main to top, eliminate macros.
This commit is contained in:
Thomas Harte
parent
439535e44b
commit
d01c306187
@ -248,13 +248,124 @@ class MemoryMap {
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uint8_t speed_register_ = 0x00;
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uint8_t speed_register_ = 0x00;
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// MARK: - Memory banking.
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// MARK: - Memory banking.
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void assert_is_region(uint8_t start, uint8_t end) {
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#define assert_is_region(start, end) \
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assert(region_map[start] == region_map[start-1]+1);
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assert(region_map[start] == region_map[start-1]+1); \
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assert(region_map[end-1] == region_map[start]);
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assert(region_map[end-1] == region_map[start]); \
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assert(region_map[end] == region_map[end-1]+1);
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assert(region_map[end] == region_map[end-1]+1);
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}
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template <int type> void set_paging() {
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template <int type> void set_paging() {
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// Establish whether main or auxiliary RAM
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// is exposed in bank $00 for a bunch of regions.
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if constexpr (type & PagingType::Main) {
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const auto set = [&](std::size_t page, const auto &flags) {
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auto ®ion = regions[region_map[page]];
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region.read = flags.read ? &ram_base[0x01'0000] : ram_base;
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region.write = flags.write ? &ram_base[0x01'0000] : ram_base;
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};
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const auto state = auxiliary_switches_.main_state();
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// Base: $0200–$03FF.
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set(0x02, state.base);
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assert_is_region(0x02, 0x04);
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// Region $0400–$07ff.
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set(0x04, state.region_04_08);
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assert_is_region(0x04, 0x08);
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// Base: $0800–$1FFF.
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set(0x08, state.base);
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assert_is_region(0x08, 0x20);
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// Region $2000–$3FFF.
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set(0x20, state.region_20_40);
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assert_is_region(0x20, 0x40);
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// Base: $4000–$BFFF.
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set(0x40, state.base);
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assert_is_region(0x40, 0xc0);
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}
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// Update whether base or auxiliary RAM is visible in: (i) the zero
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// and stack pages; and (ii) anywhere that the language card is exposing RAM instead of ROM.
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if constexpr (bool(type & PagingType::ZeroPage)) {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x01'0000] : ram_base;
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assert(region_map[0x0000] == region_map[0x0001]);
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assert(region_map[0x0001]+1 == region_map[0x0002]);
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}
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// Establish whether ROM or card switches are exposed in the distinct
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// regions C100–C2FF, C300–C3FF, C400–C7FF and C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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if constexpr (bool(type & (PagingType::CardArea | PagingType::Main))) {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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const auto apply_region = [&](bool flag, auto ®ion) {
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region.write = nullptr;
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if(flag) {
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region.read = rom;
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region.flags &= ~Region::IsIO;
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} else {
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region.flags |= Region::IsIO;
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}
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};
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc2] == region_map[bank_base | 0xc1]);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc2]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc7] == region_map[bank_base | 0xc4]);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc7]+1);
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assert(region_map[bank_base | 0xcf] == region_map[bank_base | 0xc8]);
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assert(region_map[bank_base | 0xd0] == region_map[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x01'0000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x01'0000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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// Update the region from
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// Update the region from
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// $D000 onwards as per the state of the language card flags — there may
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// $D000 onwards as per the state of the language card flags — there may
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// end up being ROM or RAM (or auxiliary RAM), and the first 4kb of it
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// end up being ROM or RAM (or auxiliary RAM), and the first 4kb of it
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@ -314,121 +425,6 @@ class MemoryMap {
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apply(0xe000, e0_ram);
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apply(0xe000, e0_ram);
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apply(0xe100, e0_ram);
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apply(0xe100, e0_ram);
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}
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}
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// Establish whether main or auxiliary RAM
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// is exposed in bank $00 for a bunch of regions.
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if constexpr (type & PagingType::Main) {
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const auto state = auxiliary_switches_.main_state();
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#define set(page, flags) {\
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auto ®ion = regions[region_map[page]]; \
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region.read = flags.read ? &ram_base[0x01'0000] : ram_base; \
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region.write = flags.write ? &ram_base[0x01'0000] : ram_base; \
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}
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// Base: $0200–$03FF.
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set(0x02, state.base);
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assert_is_region(0x02, 0x04);
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// Region $0400–$07ff.
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set(0x04, state.region_04_08);
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assert_is_region(0x04, 0x08);
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// Base: $0800–$1FFF.
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set(0x08, state.base);
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assert_is_region(0x08, 0x20);
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// Region $2000–$3FFF.
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set(0x20, state.region_20_40);
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assert_is_region(0x20, 0x40);
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// Base: $4000–$BFFF.
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set(0x40, state.base);
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assert_is_region(0x40, 0xc0);
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#undef set
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}
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// Update whether base or auxiliary RAM is visible in: (i) the zero
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// and stack pages; and (ii) anywhere that the language card is exposing RAM instead of ROM.
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if constexpr (bool(type & PagingType::ZeroPage)) {
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// Affects bank $00 only, and should be a single region.
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auto ®ion = regions[region_map[0]];
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region.read = region.write = auxiliary_switches_.zero_state() ? &ram_base[0x01'0000] : ram_base;
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assert(region_map[0x0000] == region_map[0x0001]);
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assert(region_map[0x0001]+1 == region_map[0x0002]);
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}
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// Establish whether ROM or card switches are exposed in the distinct
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// regions C100–C2FF, C300–C3FF, C400–C7FF and C800–CFFF.
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//
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// On the IIgs it intersects with the current shadow register.
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if constexpr (bool(type & (PagingType::CardArea | PagingType::Main))) {
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const bool inhibit_banks0001 = shadow_register_ & 0x40;
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const auto state = auxiliary_switches_.card_state();
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auto apply = [&state, this](uint32_t bank_base) {
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auto &c0_region = regions[region_map[bank_base | 0xc0]];
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auto &c1_region = regions[region_map[bank_base | 0xc1]];
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auto &c3_region = regions[region_map[bank_base | 0xc3]];
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auto &c4_region = regions[region_map[bank_base | 0xc4]];
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auto &c8_region = regions[region_map[bank_base | 0xc8]];
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const uint8_t *const rom = ®ions[region_map[0xffd0]].read[0xffc100] - ((bank_base << 8) + 0xc100);
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// This is applied dynamically as it may be added or lost in banks $00 and $01.
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c0_region.flags |= Region::IsIO;
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#define apply_region(flag, region) \
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region.write = nullptr; \
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if(flag) { \
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region.read = rom; \
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region.flags &= ~Region::IsIO; \
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} else { \
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region.flags |= Region::IsIO; \
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}
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apply_region(state.region_C1_C3, c1_region);
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apply_region(state.region_C3, c3_region);
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apply_region(state.region_C4_C8, c4_region);
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apply_region(state.region_C8_D0, c8_region);
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#undef apply_region
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// Sanity checks.
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assert(region_map[bank_base | 0xc1] == region_map[bank_base | 0xc0]+1);
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assert(region_map[bank_base | 0xc2] == region_map[bank_base | 0xc1]);
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assert(region_map[bank_base | 0xc3] == region_map[bank_base | 0xc2]+1);
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assert(region_map[bank_base | 0xc4] == region_map[bank_base | 0xc3]+1);
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assert(region_map[bank_base | 0xc7] == region_map[bank_base | 0xc4]);
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assert(region_map[bank_base | 0xc8] == region_map[bank_base | 0xc7]+1);
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assert(region_map[bank_base | 0xcf] == region_map[bank_base | 0xc8]);
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assert(region_map[bank_base | 0xd0] == region_map[bank_base | 0xcf]+1);
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};
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if(inhibit_banks0001) {
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// Set no IO in the Cx00 range for banks $00 and $01, just
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// regular RAM (or possibly auxiliary).
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const auto auxiliary_state = auxiliary_switches_.main_state();
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for(uint8_t region = region_map[0x00c0]; region < region_map[0x00d0]; region++) {
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regions[region].read = auxiliary_state.base.read ? &ram_base[0x01'0000] : ram_base;
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regions[region].write = auxiliary_state.base.write ? &ram_base[0x01'0000] : ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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for(uint8_t region = region_map[0x01c0]; region < region_map[0x01d0]; region++) {
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regions[region].read = regions[region].write = ram_base;
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regions[region].flags &= ~Region::IsIO;
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}
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} else {
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// Obey the card state for banks $00 and $01.
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apply(0x0000);
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apply(0x0100);
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}
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// Obey the card state for banks $e0 and $e1.
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apply(0xe000);
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apply(0xe100);
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}
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}
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}
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// IIgs specific: sets or resets the ::IsShadowed flag across affected banks as
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// IIgs specific: sets or resets the ::IsShadowed flag across affected banks as
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@ -563,8 +559,6 @@ class MemoryMap {
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}
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}
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}
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}
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#undef assert_is_region
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private:
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private:
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// Various precomputed bitsets describing key regions; std::bitset doesn't support constexpr instantiation
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// Various precomputed bitsets describing key regions; std::bitset doesn't support constexpr instantiation
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// beyond the first 64 bits at the time of writing, alas, so these are generated at runtime.
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// beyond the first 64 bits at the time of writing, alas, so these are generated at runtime.
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