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Port BSR, BTST.

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This commit is contained in:
Thomas Harte 2022-04-24 20:49:41 -04:00
parent 03caa53863
commit d01fa96177
1 changed files with 18 additions and 22 deletions
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40
InstructionSets/68k/Decoder.cpp
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@ -228,8 +228,9 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
AlterableAddressingModes AlterableAddressingModes
>::value; >::value;
case OpT(Operation::Bccw): case OpT(Operation::Bccl):
case OpT(Operation::ANDItoCCR): case OpT(Operation::ANDItoCCR):
case OpT(Operation::Bccw): case OpT(Operation::Bccl):
case OpT(Operation::BSRl): case OpT(Operation::BSRw):
return ~OneOperandMask< return ~OneOperandMask<
Imm Imm
>::value; >::value;
@ -242,6 +243,7 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
>::value; >::value;
case OpT(Operation::Bccb): case OpT(Operation::Bccb):
case OpT(Operation::BSRb):
return ~OneOperandMask< return ~OneOperandMask<
Quick Quick
>::value; >::value;
@ -260,6 +262,18 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
AlterableAddressingModesNoAn AlterableAddressingModesNoAn
>::value; >::value;
case OpT(Operation::BTST):
return ~TwoOperandMask<
Dn,
AllModesNoAn
>::value;
case BTSTI:
return ~TwoOperandMask<
Imm,
Dn | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn
>::value;
case OpT(Operation::NBCD): case OpT(Operation::NBCD):
return ~OneOperandMask< return ~OneOperandMask<
AlterableAddressingModesNoAn AlterableAddressingModesNoAn
@ -297,6 +311,8 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
case OpT(Operation::BCHG): case BCHGI: case OpT(Operation::BCHG): case BCHGI:
case OpT(Operation::BCLR): case BCLRI: case OpT(Operation::BCLR): case BCLRI:
case OpT(Operation::BSET): case BSETI: case OpT(Operation::BSET): case BSETI:
case OpT(Operation::BSRb): case OpT(Operation::BSRw): case OpT(Operation::BSRl):
case OpT(Operation::BTST): case BTSTI:
case OpT(Operation::NBCD): { case OpT(Operation::NBCD): {
const auto invalid = invalid_operands<op>(); const auto invalid = invalid_operands<op>();
const auto observed = operand_mask(original); const auto observed = operand_mask(original);
@ -395,8 +411,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
} }
} }
case SUBtoRb: case SUBtoRw: case SUBtoRl: case SUBtoRb: case SUBtoRw: case SUBtoRl: {
/*case ADDtoRb: case ADDtoRw: case ADDtoRl: */{
constexpr bool is_byte = op == ADDtoRb || op == SUBtoRb || op == SUBtoRb || op == ADDtoRb; constexpr bool is_byte = op == ADDtoRb || op == SUBtoRb || op == SUBtoRb || op == ADDtoRb;
switch(original.mode<0>()) { switch(original.mode<0>()) {
@ -511,25 +526,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
return Preinstruction(); return Preinstruction();
} }
case OpT(Operation::BTST):
switch(original.mode<1>()) {
default: return original;
case AddressingMode::None:
case AddressingMode::AddressRegisterDirect:
return Preinstruction();
}
case BTSTI:
switch(original.mode<1>()) {
default: return original;
case AddressingMode::None:
case AddressingMode::AddressRegisterDirect:
case AddressingMode::ImmediateData:
return Preinstruction();
}
case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl): case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl):
switch(original.mode<0>()) { switch(original.mode<0>()) {
default: return original; default: return original;