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Step gingerly on to fetching operands.

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This commit is contained in:
Thomas Harte 2022-05-17 08:26:35 -04:00
parent 2147c5a5f2
commit d0b6451f02
2 changed files with 27 additions and 5 deletions
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25
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -142,8 +142,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// Reads one futher word from the program counter and inserts it into // Reads one futher word from the program counter and inserts it into
// the prefetch queue. // the prefetch queue.
#define Prefetch() \ #define Prefetch() \
prefetch_[0] = prefetch_[1]; \ prefetch_.high = prefetch_.low; \
ReadProgramWord(prefetch_[1]) ReadProgramWord(prefetch_.low)
// Otherwise continue for all time, until back in debt. // Otherwise continue for all time, until back in debt.
// Formatting is slightly obtuse here to make this look more like a coroutine. // Formatting is slightly obtuse here to make this look more like a coroutine.
@ -173,9 +173,28 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
IdleBus(1); // n IdleBus(1); // n
Prefetch(); // np Prefetch(); // np
MoveToState(State::Dispatch); MoveToState(State::Decode);
break; break;
// Inspect the prefetch queue in order to decode the next instruction,
// and segue into the fetching of operands.
case State::Decode:
opcode_ = prefetch_.high.w;
instruction_ = decoder_.decode(opcode_);
// TODO: it might be better to switch on instruction_.operation
// and establish both the instruction pattern and the operand
// flags here?
operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000>(instruction_.operation);
operand_ = 0;
[[fallthrough]];
// Check the operand flags to determine whether the operand at index
// operand_ needs to be fetched, and do so.
case State::FetchOperand:
[[fallthrough]];
default: default:
assert(false); assert(false);
}} }}

7
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
View File

@ -18,8 +18,9 @@ namespace MC68000Mk2 {
struct ProcessorBase { struct ProcessorBase {
enum State: int { enum State: int {
Reset = -1, Reset = -1,
Dispatch = -2, Decode = -2,
WaitForDTACK = -3, WaitForDTACK = -3,
FetchOperand = -4,
}; };
int state_ = State::Reset; int state_ = State::Reset;
@ -30,6 +31,7 @@ struct ProcessorBase {
InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_; InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
InstructionSet::M68k::Preinstruction instruction_; InstructionSet::M68k::Preinstruction instruction_;
uint16_t opcode_; uint16_t opcode_;
uint8_t operand_flags_;
InstructionSet::M68k::Status status_; InstructionSet::M68k::Status status_;
SlicedInt32 program_counter_; SlicedInt32 program_counter_;
@ -40,7 +42,8 @@ struct ProcessorBase {
bool vpa_ = false; bool vpa_ = false;
bool berr_ = false; bool berr_ = false;
SlicedInt16 prefetch_[2]; SlicedInt32 prefetch_;
int operand_ = 0;
}; };
} }