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Step gingerly on to fetching operands.
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2147c5a5f2
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@ -142,8 +142,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Reads one futher word from the program counter and inserts it into
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// the prefetch queue.
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#define Prefetch() \
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prefetch_[0] = prefetch_[1]; \
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ReadProgramWord(prefetch_[1])
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prefetch_.high = prefetch_.low; \
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ReadProgramWord(prefetch_.low)
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// Otherwise continue for all time, until back in debt.
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// Formatting is slightly obtuse here to make this look more like a coroutine.
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@ -173,9 +173,28 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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IdleBus(1); // n
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Prefetch(); // np
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MoveToState(State::Dispatch);
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MoveToState(State::Decode);
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break;
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// Inspect the prefetch queue in order to decode the next instruction,
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// and segue into the fetching of operands.
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case State::Decode:
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opcode_ = prefetch_.high.w;
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instruction_ = decoder_.decode(opcode_);
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// TODO: it might be better to switch on instruction_.operation
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// and establish both the instruction pattern and the operand
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// flags here?
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operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000>(instruction_.operation);
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operand_ = 0;
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[[fallthrough]];
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// Check the operand flags to determine whether the operand at index
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// operand_ needs to be fetched, and do so.
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case State::FetchOperand:
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[[fallthrough]];
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default:
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assert(false);
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}}
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@ -18,8 +18,9 @@ namespace MC68000Mk2 {
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struct ProcessorBase {
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enum State: int {
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Reset = -1,
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Dispatch = -2,
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Decode = -2,
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WaitForDTACK = -3,
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FetchOperand = -4,
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};
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int state_ = State::Reset;
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@ -30,6 +31,7 @@ struct ProcessorBase {
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InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
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InstructionSet::M68k::Preinstruction instruction_;
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uint16_t opcode_;
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uint8_t operand_flags_;
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InstructionSet::M68k::Status status_;
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SlicedInt32 program_counter_;
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@ -40,7 +42,8 @@ struct ProcessorBase {
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bool vpa_ = false;
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bool berr_ = false;
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SlicedInt16 prefetch_[2];
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SlicedInt32 prefetch_;
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int operand_ = 0;
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};
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}
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