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For now, assume the .q actions can be handled inside Preinstruction.

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This commit is contained in:
Thomas Harte 2022-04-13 09:29:12 -04:00
parent cc4431c409
commit d1613025ee
3 changed files with 36 additions and 12 deletions
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21
InstructionSets/68k/Decoder.cpp
View File

@ -24,6 +24,12 @@ constexpr AddressingMode combined_mode(int mode, int reg) {
// MARK: - Instruction decoders.
/// Maps from an ExtendedOperation to an Operation; in practice that means that anything
/// that already is an Operation is passed through, and other things are mapped down into
/// an operation that doesn't duplicate detail about the operands that can be held by a
/// Preinstruction in other ways — for example, ANDI and AND are both represented by
/// a Preinstruction with an operation of AND, the former just happens to specify an
/// immediate operand.
constexpr Operation Predecoder::operation(uint8_t op) {
if(op < uint8_t(Operation::Max)) {
return Operation(op);
@ -59,6 +65,7 @@ template <uint8_t op> Preinstruction Predecoder::decode(uint16_t instruction) {
//
// MARK: ABCD, SBCD.
//
// 4-3 (p107), 4-171 (p275)
case uint8_t(Operation::ABCD): case uint8_t(Operation::SBCD): {
const auto addressing_mode = (instruction & 8) ?
AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect;
@ -383,14 +390,14 @@ Preinstruction Predecoder::decode4(uint16_t instruction) {
Preinstruction Predecoder::decode5(uint16_t instruction) {
switch(instruction & 0x1c0) {
// 4-11 (p115)
case 0x000: DecodeOp(ADDQb);
case 0x040: DecodeOp(ADDQw);
case 0x080: DecodeOp(ADDQl);
case 0x000: DecodeEop(ADDQb);
case 0x040: DecodeEop(ADDQw);
case 0x080: DecodeEop(ADDQl);
// 4-181 (p285)
case 0x100: DecodeOp(SUBQb);
case 0x140: DecodeOp(SUBQw);
case 0x180: DecodeOp(SUBQl);
case 0x100: DecodeEop(SUBQb);
case 0x140: DecodeEop(SUBQw);
case 0x180: DecodeEop(SUBQl);
default: break;
}
@ -411,7 +418,7 @@ Preinstruction Predecoder::decode6(uint16_t instruction) {
Preinstruction Predecoder::decode7(uint16_t instruction) {
// 4-134 (p238)
DecodeOp(MOVEq);
DecodeEop(MOVEq);
}
Preinstruction Predecoder::decode8(uint16_t instruction) {

6
InstructionSets/68k/Decoder.hpp
View File

@ -53,6 +53,12 @@ class Predecoder {
MOVEPtoRl, MOVEPtoRw,
MOVEPtoMl, MOVEPtoMw,
ADDQb, ADDQw, ADDQl,
ADDQAw, ADDQAl,
SUBQb, SUBQw, SUBQl,
SUBQAw, SUBQAl,
MOVEq,
};
static constexpr Operation operation(uint8_t op);
};

21
InstructionSets/68k/Instruction.hpp
View File

@ -22,18 +22,14 @@ enum class Operation: uint8_t {
ABCD, SBCD, NBCD,
ADDb, ADDw, ADDl,
ADDQb, ADDQw, ADDQl,
ADDAw, ADDAl,
ADDQAw, ADDQAl,
ADDXb, ADDXw, ADDXl,
SUBb, SUBw, SUBl,
SUBQb, SUBQw, SUBQl,
SUBAw, SUBAl,
SUBQAw, SUBQAl,
SUBXb, SUBXw, SUBXl,
MOVEb, MOVEw, MOVEl, MOVEq,
MOVEb, MOVEw, MOVEl,
MOVEAw, MOVEAl,
PEA,
@ -101,6 +97,18 @@ enum class Operation: uint8_t {
Max = RESET
};
constexpr int size(Operation operation) {
// TODO: most of this table, once I've settled on what stays in
// the Operation table and what doesn't.
switch(operation) {
case Operation::ADDb: case Operation::ADDXb:
case Operation::SUBb: case Operation::SUBXb:
return 1;
default: return 0;
}
}
/// Indicates the addressing mode applicable to an operand.
///
/// Implementation notes:
@ -167,6 +175,9 @@ enum class AddressingMode: uint8_t {
/// #
ImmediateData = 0b01'100,
/// .q; value is provided as the corresponding 'reg'.
Quick = 0b11'110,
};
/*!