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Accept the C++ I'm in; clarify and simplify interface.
This commit is contained in:
Thomas Harte
parent
f9cbec668b
commit
d205e538e1
@ -17,49 +17,39 @@ enum class Model {
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};
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enum class Operation {
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/// Rd = Op1 AND Op2.
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AND,
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/// Rd = Op1 EOR Op2.
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EOR,
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/// Rd = Op1 - Op2.
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SUB,
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/// Rd = Op2 - Op1.
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RSB,
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/// Rd = Op1 + Op2.
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ADD,
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/// Rd = Op1 + Ord2 + C.
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ADC,
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/// Rd = Op1 - Op2 + C.
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SBC,
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/// Rd = Op2 - Op1 + C.
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RSC,
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/// Set condition codes on Op1 AND Op2.
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TST,
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/// Set condition codes on Op1 EOR Op2.
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TEQ,
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/// Set condition codes on Op1 - Op2.
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CMP,
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/// Set condition codes on Op1 + Op2.
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CMN,
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/// Rd = Op1 OR Op2.
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ORR,
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/// Rd = Op2
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MOV,
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/// Rd = Op1 AND NOT Op2.
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BIC,
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/// Rd = NOT Op2.
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MVN,
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AND, /// Rd = Op1 AND Op2.
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EOR, /// Rd = Op1 EOR Op2.
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SUB, /// Rd = Op1 - Op2.
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RSB, /// Rd = Op2 - Op1.
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ADD, /// Rd = Op1 + Op2.
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ADC, /// Rd = Op1 + Ord2 + C.
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SBC, /// Rd = Op1 - Op2 + C.
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RSC, /// Rd = Op2 - Op1 + C.
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TST, /// Set condition codes on Op1 AND Op2.
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TEQ, /// Set condition codes on Op1 EOR Op2.
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CMP, /// Set condition codes on Op1 - Op2.
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CMN, /// Set condition codes on Op1 + Op2.
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ORR, /// Rd = Op1 OR Op2.
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MOV, /// Rd = Op2
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BIC, /// Rd = Op1 AND NOT Op2.
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MVN, /// Rd = NOT Op2.
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MUL, MLA,
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B, BL,
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MUL, /// Rd = Rm * Rs
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MLA, /// Rd = Rm * Rs + Rn
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B, /// Add offset to PC; programmer allows for PC being two words ahead.
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BL, /// Copy PC and PSR to R14, then branch. Copied PC points to next instruction.
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LDR, STR,
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LDM, STM,
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SWI,
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LDR, /// Read single byte or word from [base + offset], possibly mutating the base.
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STR, /// Write a single byte or word to [base + offset], possibly mutating the base.
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LDM, /// Read 1–16 words from [base], possibly mutating it.
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STM, /// Write 1-16 words to [base], possibly mutating it.
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SWI, /// Perform a software interrupt.
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CDP,
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MRC, MCR,
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LDC, STC,
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CDP, /// Coprocessor data operation.
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MRC, /// Move from coprocessor register to ARM register.
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MCR, /// Move from ARM register to coprocessor register.
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LDC, /// Coprocessor data transfer load.
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STC, /// Coprocessor data transfer store.
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Undefined,
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};
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@ -78,8 +68,11 @@ enum class ShiftType {
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RotateRight = 0b11,
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};
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//
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// Implementation details.
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//
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static constexpr int FlagsStartBit = 20;
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using Flags = uint8_t;
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template <int position>
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constexpr bool flag_bit(uint8_t flags) {
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@ -105,6 +98,19 @@ protected:
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uint32_t opcode_;
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};
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//
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// Branch (i.e. B and BL).
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//
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struct Branch {
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constexpr Branch(uint32_t opcode) noexcept : opcode_(opcode) {}
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/// The 26-bit offset to add to the PC.
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int offset() const { return (opcode_ & 0xff'ffff) << 2; }
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private:
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uint32_t opcode_;
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};
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//
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// Data processing (i.e. AND to MVN).
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//
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@ -229,7 +235,7 @@ struct BlockDataTransfer: public WithShiftControlBits {
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};
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//
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// Coprocessor data operation and register transfer.
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// Coprocessor data operation.
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//
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struct CoprocessorDataOperationFlags {
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constexpr CoprocessorDataOperationFlags(uint8_t flags) noexcept : flags_(flags) {}
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@ -240,6 +246,22 @@ private:
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uint8_t flags_;
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};
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struct CoprocessorDataOperation {
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constexpr CoprocessorDataOperation(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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int destination() { return (opcode_ >> 12) & 0xf; }
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int coprocessor() { return (opcode_ >> 8) & 0xf; }
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int information() { return (opcode_ >> 5) & 0x7; }
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private:
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uint32_t opcode_;
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};
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//
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// Coprocessor register transfer.
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//
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struct CoprocessorRegisterTransferFlags {
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constexpr CoprocessorRegisterTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
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@ -249,8 +271,8 @@ private:
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uint8_t flags_;
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};
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struct CoprocessorOperationOrRegisterTransfer {
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constexpr CoprocessorOperationOrRegisterTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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struct CoprocessorRegisterTransfer {
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constexpr CoprocessorRegisterTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
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int operand1() { return (opcode_ >> 16) & 0xf; }
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int operand2() { return opcode_ & 0xf; }
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@ -306,103 +328,134 @@ struct OperationMapper {
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// Data processing; cf. p.17.
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if constexpr (((partial >> 26) & 0b11) == 0b00) {
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constexpr auto operation = Operation(int(Operation::AND) + ((partial >> 21) & 0xf));
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constexpr auto flags = DataProcessingFlags(i);
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scheduler.template data_processing<operation, flags>(
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scheduler.template perform<operation, i>(
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condition,
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DataProcessing(instruction)
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);
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return;
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}
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// Multiply and multiply-accumulate (MUL, MLA); cf. p.23.
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if constexpr (((partial >> 22) & 0b111'111) == 0b000'000) {
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// This implementation provides only eight bits baked into the template parameters so
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// an additional dynamic test is required to check whether this is really, really MUL or MLA.
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if(((instruction >> 4) & 0b1111) != 0b1001) {
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scheduler.unknown(instruction);
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} else {
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if(((instruction >> 4) & 0b1111) == 0b1001) {
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constexpr bool is_mla = partial & (1 << 21);
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constexpr auto flags = MultiplyFlags(i);
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scheduler.template multiply<is_mla ? Operation::MLA : Operation::MUL, flags>(
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scheduler.template perform<is_mla ? Operation::MLA : Operation::MUL, i>(
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condition,
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Multiply(instruction)
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);
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return;
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}
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}
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// Single data transfer (LDR, STR); cf. p.25.
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if constexpr (((partial >> 26) & 0b11) == 0b01) {
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constexpr bool is_ldr = partial & (1 << 20);
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constexpr auto flags = SingleDataTransferFlags(i);
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scheduler.template single_data_transfer<is_ldr ? Operation::LDR : Operation::STR, flags>(
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scheduler.template perform<is_ldr ? Operation::LDR : Operation::STR, i>(
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condition,
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SingleDataTransfer(instruction)
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);
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return;
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}
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// Block data transfer (LDM, STM); cf. p.29.
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if constexpr (((partial >> 25) & 0b111) == 0b100) {
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constexpr bool is_ldm = partial & (1 << 20);
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constexpr auto flags = BlockDataTransferFlags(i);
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scheduler.template block_data_transfer<is_ldm ? Operation::LDM : Operation::STM, flags>(
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scheduler.template perform<is_ldm ? Operation::LDM : Operation::STM, i>(
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condition,
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BlockDataTransfer(instruction)
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);
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return;
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}
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// Branch and branch with link (B, BL); cf. p.15.
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if constexpr (((partial >> 25) & 0b111) == 0b101) {
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constexpr bool is_bl = partial & (1 << 24);
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scheduler.template branch<is_bl ? Operation::BL : Operation::B>(
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scheduler.template perform<is_bl ? Operation::BL : Operation::B>(
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condition,
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(instruction & 0xf'ffff) << 2
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Branch(instruction)
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);
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return;
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}
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// Software interreupt; cf. p.35.
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if constexpr (((partial >> 24) & 0b1111) == 0b1111) {
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scheduler.software_interrupt(condition);
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return;
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}
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// Both:
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// Coprocessor data operation; cf. p. 37; and
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// Coprocessor register transfers; cf. p. 42.
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if constexpr (((partial >> 24) & 0b1111) == 0b1110) {
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const auto parameters = CoprocessorOperationOrRegisterTransfer(instruction);
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// TODO: parameters should probably vary.
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if(instruction & (1 << 4)) {
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// Register transfer.
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constexpr auto flags = CoprocessorRegisterTransferFlags(i);
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const auto parameters = CoprocessorRegisterTransfer(instruction);
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constexpr bool is_mrc = partial & (1 << 20);
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scheduler.template coprocessor_register_transfer<is_mrc ? Operation::MRC : Operation::MCR, flags>(
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scheduler.template perform<is_mrc ? Operation::MRC : Operation::MCR, i>(
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condition,
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parameters
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);
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} else {
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// Data operation.
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constexpr auto flags = CoprocessorDataOperationFlags(i);
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scheduler.template coprocessor_data_operation<flags>(
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const auto parameters = CoprocessorDataOperation(instruction);
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scheduler.template perform<i>(
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condition,
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parameters
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);
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}
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return;
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}
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// Coprocessor data transfers; cf. p.39.
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if constexpr (((partial >> 25) & 0b111) == 0b110) {
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constexpr bool is_ldc = partial & (1 << 20);
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constexpr auto flags = CoprocessorDataTransferFlags(i);
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scheduler.template coprocessor_data_transfer<is_ldc ? Operation::LDC : Operation::STC, flags>(
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scheduler.template perform<is_ldc ? Operation::LDC : Operation::STC, i>(
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condition,
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CoprocessorDataTransfer(instruction)
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);
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return;
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}
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// Fallback position.
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scheduler.unknown(instruction);
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}
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};
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/// A brief documentation of the interface expected by @c dispatch below; will be a concept if/when this project adopts C++20.
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struct SampleScheduler {
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// General template arguments:
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//
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// (1) Operation, telling the function which operation to perform. Will always be from the subset
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// implied by the operation category; and
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// (2) Flags, an opaque type which can be converted into a DataProcessingFlags, MultiplyFlags, etc,
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// by simply construction, to provide all flags that can be baked into the template parameters.
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//
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// Arguments are ommitted if not relevant.
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//
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// Function arguments:
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//
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// (1) Condition, indicating the condition code associated with this operation; and
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// (2) An operation-specific encapsulation of the operation code for decoding of fields that didn't
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// fit into the template parameters.
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template <Operation, Flags> void perform(Condition, DataProcessing);
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template <Operation, Flags> void perform(Condition, Multiply);
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template <Operation, Flags> void perform(Condition, SingleDataTransfer);
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template <Operation, Flags> void perform(Condition, BlockDataTransfer);
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template <Operation> void perform(Condition, Branch);
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template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer);
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template <Flags> void perform(Condition, CoprocessorDataOperation);
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template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer);
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// Irregular operations.
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void software_interrupt(Condition);
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void unknown(uint32_t opcode);
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};
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/// Decodes @c instruction, making an appropriate call into @c scheduler.
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///
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/// In lieue of C++20, see the sample definition of SampleScheduler above for the expected interface.
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template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
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OperationMapper mapper;
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Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
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@ -12,12 +12,33 @@
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using namespace InstructionSet::ARM;
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namespace {
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struct Scheduler {
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template <Operation, Flags> void perform(Condition, DataProcessing) {}
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template <Operation, Flags> void perform(Condition, Multiply) {}
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template <Operation, Flags> void perform(Condition, SingleDataTransfer) {}
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template <Operation, Flags> void perform(Condition, BlockDataTransfer) {}
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template <Operation> void perform(Condition, Branch) {}
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template <Operation, Flags> void perform(Condition, CoprocessorRegisterTransfer) {}
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template <Flags> void perform(Condition, CoprocessorDataOperation) {}
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template<Operation, Flags> void perform(Condition, CoprocessorDataTransfer) {}
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void software_interrupt(Condition) {}
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void unknown(uint32_t) {}
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};
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}
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@interface ARMDecoderTests : XCTestCase
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@end
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@implementation ARMDecoderTests
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- (void)testXYX {
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Scheduler scheduler;
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InstructionSet::ARM::dispatch(1, scheduler);
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// const auto intr = Instruction<Model::ARM2>(1);
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// NSLog(@"%d", intr.operation());
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}
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