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Throws in official register names.
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@ -453,14 +453,6 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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fetch_vertical_ |= y_ == display_window_start_[1];
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fetch_vertical_ &= y_ != display_window_stop_[1];
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// if(y_ == display_window_start_[1]) {
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// fetch_vertical_ = true;
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//// LOG("Enabling vertical fetch at line " << std::dec << +y_);
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// }
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// if(y_ == display_window_stop_[1]) {
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// fetch_vertical_ = false;
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//// LOG("Disabling vertical fetch at line " << std::dec << +y_);
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// }
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if(did_fetch_) {
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bitplanes_.do_end_of_line();
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@ -598,11 +590,11 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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break;
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// Raster position.
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case Read(0x004): {
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case Read(0x004): { // VPOSR; b15 = LOF, b0 = b8 of y position.
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const uint16_t position = uint16_t(y_ >> 8);
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cycle.set_value16(position);
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} break;
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case Read(0x006): {
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case Read(0x006): { // VHPOSR; b0–b7 = b0–b7 of y position; b8–b15 = horizontal position.
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const uint16_t position = uint16_t(((line_cycle_ << 6) & 0xff00) | (y_ & 0x00ff));
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cycle.set_value16(position);
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} break;
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@ -615,113 +607,113 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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break;
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// Joystick/mouse input.
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case Read(0x00a):
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case Read(0x00a): // JOY0DAT
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cycle.set_value16(mouse_.get_position());
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break;
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case Read(0x00c):
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case Read(0x00c): // JOY1DAT
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cycle.set_value16(0x0202);
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break;
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case Write(0x034):
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case Write(0x034): // POTGO
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// LOG("TODO: pot port start");
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break;
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case Read(0x016):
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case Read(0x016): // POTGOR / POTINP
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// LOG("TODO: pot port read");
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cycle.set_value16(0xff00);
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break;
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// Disk DMA and control.
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case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break;
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case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break;
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case Write(0x024): disk_.set_length(cycle.value16()); break;
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case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break; // DSKPTH
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case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break; // DSKPTL
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case Write(0x024): disk_.set_length(cycle.value16()); break; // DSKLEN
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case Write(0x026):
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case Write(0x026): // DSKDAT
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x09e):
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case Write(0x09e): // ADKCON
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LOG("Write disk control");
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ApplySetClear(paula_disk_control_, 0x7fff);
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disk_controller_.set_control(paula_disk_control_);
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// TODO: should also post to Paula.
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break;
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case Read(0x010):
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case Read(0x010): // ADKCONR
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LOG("Read disk control");
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cycle.set_value16(paula_disk_control_);
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break;
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case Write(0x07e):
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case Write(0x07e): // DSKSYNC
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disk_controller_.set_sync_word(cycle.value16());
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assert(false); // Not fully implemented.
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break;
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case Read(0x01a):
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case Read(0x01a): // DSKBYTR
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LOG("TODO: disk status");
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assert(false); // Not yet implemented.
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break;
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// Refresh.
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case Write(0x028):
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case Write(0x028): // REFPTR
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Serial port.
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case Read(0x018):
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case Read(0x018): // SERDATR
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LOG("TODO: serial data and status");
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cycle.set_value16(0x3000); // i.e. transmit buffer empty.
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break;
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case Write(0x030):
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case Write(0x030): // SERDAT
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LOG("TODO: serial data: " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x032):
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case Write(0x032): // SERPER
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LOG("TODO: serial control: " << PADHEX(4) << cycle.value16());
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serial_.set_control(cycle.value16());
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break;
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// DMA management.
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case Read(0x002):
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case Read(0x002): // DMACONR
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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case Write(0x096):
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case Write(0x096): // DMACON
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ApplySetClear(dma_control_, 0x1fff);
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break;
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// Interrupts.
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case Write(0x09a):
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case Write(0x09a): // INTENA
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ApplySetClear(interrupt_enable_, 0x7fff);
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update_interrupts();
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break;
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case Read(0x01c):
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case Read(0x01c): // INTENAR
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cycle.set_value16(interrupt_enable_);
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break;
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case Write(0x09c):
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case Write(0x09c): // INTREQ
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ApplySetClear(interrupt_requests_, 0x7fff);
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update_interrupts();
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break;
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case Read(0x01e):
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case Read(0x01e): // INTREQR
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cycle.set_value16(interrupt_requests_);
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break;
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// Display management.
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case Write(0x08e): {
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case Write(0x08e): { // DIWSTRT
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const uint16_t value = cycle.value16();
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display_window_start_[0] = value & 0xff;
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display_window_start_[1] = value >> 8;
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} break;
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case Write(0x090): {
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case Write(0x090): { // DIWSTOP
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const uint16_t value = cycle.value16();
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display_window_stop_[0] = 0x100 | (value & 0xff);
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display_window_stop_[1] = value >> 8;
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display_window_stop_[1] |= ((value >> 7) & 0x100) ^ 0x100;
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} break;
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case Write(0x092):
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case Write(0x092): // DDFSTRT
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if(fetch_window_[0] != cycle.value16()) {
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LOG("Fetch window start set to " << std::dec << cycle.value16());
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}
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fetch_window_[0] = cycle.value16();
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break;
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case Write(0x094):
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case Write(0x094): // DDFSTOP
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// TODO: something in my interpretation of ddfstart and ddfstop
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// means a + 8 is needed below for high-res displays. Investigate.
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if(fetch_window_[1] != cycle.value16() + 8) {
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@ -731,41 +723,37 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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break;
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// Bitplanes.
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case Write(0x0e0): bitplanes_.set_pointer<0, 16>(cycle.value16()); break;
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case Write(0x0e2): bitplanes_.set_pointer<0, 0>(cycle.value16()); break;
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case Write(0x0e4): bitplanes_.set_pointer<1, 16>(cycle.value16()); break;
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case Write(0x0e6): bitplanes_.set_pointer<1, 0>(cycle.value16()); break;
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case Write(0x0e8): bitplanes_.set_pointer<2, 16>(cycle.value16()); break;
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case Write(0x0ea): bitplanes_.set_pointer<2, 0>(cycle.value16()); break;
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case Write(0x0ec): bitplanes_.set_pointer<3, 16>(cycle.value16()); break;
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case Write(0x0ee): bitplanes_.set_pointer<3, 0>(cycle.value16()); break;
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case Write(0x0f0): bitplanes_.set_pointer<4, 16>(cycle.value16()); break;
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case Write(0x0f2): bitplanes_.set_pointer<4, 0>(cycle.value16()); break;
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case Write(0x0f4): bitplanes_.set_pointer<5, 16>(cycle.value16()); break;
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case Write(0x0f6): bitplanes_.set_pointer<5, 0>(cycle.value16()); break;
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case Write(0x0e0): bitplanes_.set_pointer<0, 16>(cycle.value16()); break; // BPL1PTH
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case Write(0x0e2): bitplanes_.set_pointer<0, 0>(cycle.value16()); break; // BPL1PTL
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case Write(0x0e4): bitplanes_.set_pointer<1, 16>(cycle.value16()); break; // BPL2PTH
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case Write(0x0e6): bitplanes_.set_pointer<1, 0>(cycle.value16()); break; // BPL2PTL
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case Write(0x0e8): bitplanes_.set_pointer<2, 16>(cycle.value16()); break; // BPL3PTH
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case Write(0x0ea): bitplanes_.set_pointer<2, 0>(cycle.value16()); break; // BPL3PTL
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case Write(0x0ec): bitplanes_.set_pointer<3, 16>(cycle.value16()); break; // BPL4PTH
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case Write(0x0ee): bitplanes_.set_pointer<3, 0>(cycle.value16()); break; // BPL4PTL
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case Write(0x0f0): bitplanes_.set_pointer<4, 16>(cycle.value16()); break; // BPL5PTH
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case Write(0x0f2): bitplanes_.set_pointer<4, 0>(cycle.value16()); break; // BPL5PTL
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case Write(0x0f4): bitplanes_.set_pointer<5, 16>(cycle.value16()); break; // BPL6PTH
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case Write(0x0f6): bitplanes_.set_pointer<5, 0>(cycle.value16()); break; // BPL6PTL
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case Write(0x102): {
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case Write(0x100): // BPLCON0
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bitplanes_.set_control(cycle.value16());
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is_high_res_ = cycle.value16() & 0x8000;
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break;
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case Write(0x102): { // BPLCON1
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const uint8_t delay = cycle.value8_low();
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odd_delay_ = delay & 0x0f;
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even_delay_ = delay >> 4;
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} break;
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case Write(0x100):
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bitplanes_.set_control(cycle.value16());
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is_high_res_ = cycle.value16() & 0x8000;
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break;
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case Write(0x104):
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case Write(0x106):
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case Write(0x104): // BPLCON2
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case Write(0x106): // BPLCON3 (ECS)
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LOG("TODO: Bitplane control; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x108):
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bitplanes_.set_modulo<0>(cycle.value16());
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break;
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case Write(0x10a):
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bitplanes_.set_modulo<1>(cycle.value16());
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break;
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case Write(0x108): bitplanes_.set_modulo<0>(cycle.value16()); break; // BPL1MOD
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case Write(0x10a): bitplanes_.set_modulo<1>(cycle.value16()); break; // BPL2MOD
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case Write(0x110):
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case Write(0x112):
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@ -827,21 +815,11 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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break;
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// Copper.
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case Write(0x02e):
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copper_.set_control(cycle.value16());
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break;
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case Write(0x080):
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copper_.set_pointer<0, 16>(cycle.value16());
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break;
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case Write(0x082):
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copper_.set_pointer<0, 0>(cycle.value16());
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break;
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case Write(0x084):
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copper_.set_pointer<1, 16>(cycle.value16());
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break;
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case Write(0x086):
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copper_.set_pointer<1, 0>(cycle.value16());
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break;
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case Write(0x02e): copper_.set_control(cycle.value16()); break; // COPCON
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case Write(0x080): copper_.set_pointer<0, 16>(cycle.value16()); break; // COP1LCH
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case Write(0x082): copper_.set_pointer<0, 0>(cycle.value16()); break; // COP1LCL
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case Write(0x084): copper_.set_pointer<1, 16>(cycle.value16()); break; // COP2LCH
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case Write(0x086): copper_.set_pointer<1, 0>(cycle.value16()); break; // COP2LCL
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case Write(0x088): case Read(0x088):
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copper_.reload<0>();
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break;
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@ -881,8 +859,6 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
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case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
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case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): {
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// LOG("Colour palette; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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// Store once in regular, linear order.
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const auto entry_address = (register_address - 0x180) >> 1;
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uint8_t *const entry = reinterpret_cast<uint8_t *>(&palette_[entry_address]);
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