6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity

Corrected simple logging error. Which mysteriously moves me all the way up to 117 failures (!)

Browse Source
This commit is contained in:
Thomas Harte 2017-05-29 16:35:00 -04:00
parent a6a4c5a936
commit d290e3d99e
2 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
OSBindings/Mac/Clock SignalTests/FUSETests.swift
View File

@ -167,7 +167,7 @@ class FUSETests: XCTestCase {
let name = itemDictionary["name"] as! String let name = itemDictionary["name"] as! String
// if name != "dd36" { // if name != "66" {
// continue; // continue;
// } // }
@ -253,7 +253,7 @@ class FUSETests: XCTestCase {
capturedBusActivity[capturedBusAcivityIndex].value == value! && capturedBusActivity[capturedBusAcivityIndex].value == value! &&
capturedBusActivity[capturedBusAcivityIndex].timeStamp == time && capturedBusActivity[capturedBusAcivityIndex].timeStamp == time &&
capturedBusActivity[capturedBusAcivityIndex].operation == operation, capturedBusActivity[capturedBusAcivityIndex].operation == operation,
"Failed bus operation match \(name)") "Failed bus operation match \(name) (at time \(time) with address \(address), value was \(value != nil ? value! : 0), tracking index \(capturedBusAcivityIndex) amgonst \(capturedBusActivity))")
capturedBusAcivityIndex += 1 capturedBusAcivityIndex += 1
} }
} }

11
Processors/Z80/Z80AllRAM.cpp
View File

@ -14,17 +14,18 @@ using namespace CPU::Z80;
AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {} AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) { int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
uint16_t address = cycle->address ? *cycle->address : 0x0000;
switch(cycle->operation) { switch(cycle->operation) {
case BusOperation::ReadOpcode: case BusOperation::ReadOpcode:
// printf("%04x %02x [BC=%02x]\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::BC)); // printf("%04x %02x [BC=%02x]\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::BC));
check_address_for_trap(*cycle->address); check_address_for_trap(address);
case BusOperation::Read: case BusOperation::Read:
// printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer)); // printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));
*cycle->value = memory_[*cycle->address]; *cycle->value = memory_[address];
break; break;
case BusOperation::Write: case BusOperation::Write:
// printf("w %04x\n", *cycle->address); // printf("w %04x\n", *cycle->address);
memory_[*cycle->address] = *cycle->value; memory_[address] = *cycle->value;
break; break;
case BusOperation::Output: case BusOperation::Output:
@ -32,7 +33,7 @@ int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
case BusOperation::Input: case BusOperation::Input:
// This logic is selected specifically because it seems to match // This logic is selected specifically because it seems to match
// the FUSE unit tests. It might need factoring out. // the FUSE unit tests. It might need factoring out.
*cycle->value = (*cycle->address) >> 8; *cycle->value = address >> 8;
break; break;
case BusOperation::Internal: case BusOperation::Internal:
@ -45,7 +46,7 @@ int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
timestamp_ += cycle->length; timestamp_ += cycle->length;
if(delegate_ != nullptr) { if(delegate_ != nullptr) {
delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle->operation, cycle->address ? *cycle->address : 0x0000, cycle->value ? *cycle->value : 0x00, timestamp_); delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle->operation, address, cycle->value ? *cycle->value : 0x00, timestamp_);
} }
return 0; return 0;