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Adds (d), y; [d], y; and [d].
Now covered: 146/256 opcodes, 4/7 pages, 25/47 bus programs.
This commit is contained in:
Thomas Harte
parent
3fc649359a
commit
d2e868ea2b
@ -160,7 +160,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationConstructAbsolute); // Calculate data address.
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read_write(type, is8bit, target);
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};
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}
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// 1b. Absolute; a, JMP.
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -168,7 +168,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPC); // New PCH.
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // [JMP]
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};
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}
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// 1c. Absolute; a, JSR.
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static void absolute_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -179,7 +179,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationPerform); // [JSR]
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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};
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}
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// 1d. Absolute; a, read-modify-write.
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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@ -188,7 +188,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationConstructAbsolute); // Calculate data address.
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read_modify_write(is8bit, target);
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};
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}
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// 2a. Absolute Indexed Indirect; (a, x), JMP.
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static void absolute_indexed_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -199,7 +199,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchIncrementData); // New PCL
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target(CycleFetchData); // New PCH.
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target(OperationPerform); // [JMP]
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};
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}
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// 2b. Absolute Indexed Indirect; (a, x), JSR.
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static void absolute_indexed_indirect_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -229,7 +229,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchData); // New PBR
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target(OperationPerform); // [JML]
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};
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}
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// 3b. Absolute Indirect; (a), JMP.
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static void absolute_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -241,7 +241,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchData); // New PCH
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target(OperationPerform); // [JMP]
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};
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}
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// 4a. Absolute long; al.
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static void absolute_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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@ -252,7 +252,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationConstructAbsolute); // Calculate data address.
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read_write(type, is8bit, target);
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};
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}
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// 4b. Absolute long; al, JMP.
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static void absolute_long_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -262,7 +262,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // ['JMP' (though it's JML in internal terms)]
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};
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}
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// 4c. Absolute long al, JSL.
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static void absolute_long_jsl(AccessType, bool, const std::function<void(MicroOp)> &target) {
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@ -280,7 +280,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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};
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}
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// 5. Absolute long, X; al, x.
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static void absolute_long_x(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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@ -373,7 +373,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPC); // IO.
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read_write(type, is8bit, target);
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};
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}
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// 10b. Direct; d, read-modify-write.
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// (That's zero page in 6502 terms)
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@ -384,7 +384,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPC); // IO.
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read_modify_write(is8bit, target);
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};
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}
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// 11. Direct Indexed Indirect; (d, x).
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static void direct_indexed_indirect(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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@ -396,7 +396,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPC); // IO.
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read_write(type, is8bit, target);
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};
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}
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// 12. Direct Indirect; (d).
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static void direct_indirect(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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@ -406,11 +406,60 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
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target(CycleFetchPC); // IO.
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read_write(type, is8bit, target);
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};
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}
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// 13. Direct Indirect Indexed; (d), y.
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static void direct_indirect_indexed(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // DO.
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target(OperationConstructDirectIndirect);
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target(CycleFetchPC); // IO.
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target(CycleFetchIncrementData); // AAL.
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target(CycleFetchData); // AAH.
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target(OperationConstructDirectIndirectIndexed);
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target(CycleFetchIncorrectDataAddress); // IO.
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read_write(type, is8bit, target);
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}
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// TODO: verify, especially re: false addresses.
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// i.e. it currently looks to me superficially as though I can reuse
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// OperationConstructDirectIndirect here, but writing the proper
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// interpreter will help to clarify.
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// 14. Direct Indirect Indexed Long; [d], y.
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static void direct_indirect_indexed_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // DO.
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target(OperationConstructDirectIndirect);
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target(CycleFetchPC); // IO.
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target(CycleFetchIncrementData); // AAL.
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target(CycleFetchIncrementData); // AAH.
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target(CycleFetchData); // AAB.
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target(OperationConstructDirectIndirectIndexedLong);
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read_write(type, is8bit, target);
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}
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// 15. Direct Indirect Long; [d].
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static void direct_indirect_long(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // DO.
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target(OperationConstructDirectIndirect);
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target(CycleFetchPC); // IO.
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target(CycleFetchIncrementData); // AAL.
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target(CycleFetchIncrementData); // AAH.
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target(CycleFetchData); // AAB.
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target(OperationConstructDirectIndirectLong);
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read_write(type, is8bit, target);
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}
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// 16a. Direct, X; d, x.
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// 16b. Direct, X; d, x, read-modify-write.
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// 17. Direct, Y; d, y.
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@ -451,7 +500,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x04 TSB d */ op(direct_rmw, TSB);
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/* 0x05 ORA d */ op(direct, ORA);
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/* 0x06 ASL d */ op(direct_rmw, ASL);
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/* 0x07 ORA [d] */
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/* 0x07 ORA [d] */ op(direct_indirect_long, ORA);
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/* 0x08 PHP s */
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/* 0x09 ORA # */
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/* 0x0a ASL A */ op(accumulator, ASL);
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@ -462,13 +511,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x0f ORA al */ op(absolute_long, ORA);
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/* 0x10 BPL r */
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/* 0x11 ORA (d), y */
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/* 0x11 ORA (d), y */ op(direct_indirect_indexed, ORA);
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/* 0x12 ORA (d) */ op(direct_indirect, ORA);
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/* 0x13 ORA (d, s), y */
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/* 0x14 TRB d */ op(absolute_rmw, TRB);
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/* 0x15 ORA d, x */
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/* 0x16 ASL d, x */
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/* 0x17 ORA [d], y */
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/* 0x17 ORA [d], y */ op(direct_indirect_indexed_long, ORA);
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/* 0x18 CLC i */
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/* 0x19 ORA a, y */ op(absolute_y, ORA);
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/* 0x1a INC A */ op(accumulator, INC);
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@ -479,13 +528,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x1f ORA al, x */ op(absolute_long_x, ORA);
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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/* 0x21 ORA (d), y */
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/* 0x22 AND (d, x) */ op(direct_indexed_indirect, AND);
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/* 0x23 JSL al */ op(absolute_long_jsl, JSL);
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/* 0x21 AND (d, x) */ op(direct_indexed_indirect, AND);
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/* 0x22 JSL al */ op(absolute_long_jsl, JSL);
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/* 0x23 AND d, s */
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/* 0x24 BIT d */ op(direct, BIT);
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/* 0x25 AND d */ op(direct, AND);
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/* 0x26 ROL d */ op(absolute_rmw, ROL);
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/* 0x27 AND [d] */
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/* 0x27 AND [d] */ op(direct_indirect_long, AND);
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/* 0x28 PLP s */
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/* 0x29 AND # */
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/* 0x2a ROL A */ op(accumulator, ROL);
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@ -496,13 +545,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x2f AND al */ op(absolute_long, AND);
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/* 0x30 BMI R */
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/* 0x31 AND (d), y */
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/* 0x31 AND (d), y */ op(direct_indirect_indexed, AND);
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/* 0x32 AND (d) */ op(direct_indirect, AND);
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/* 0x33 AND (d, s), y */
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/* 0x34 BIT d, x */
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/* 0x35 AND d, x */
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/* 0x36 ROL d, x */ op(absolute_x_rmw, ROL);
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/* 0x37 AND [d], y */
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/* 0x37 AND [d], y */ op(direct_indirect_indexed_long, AND);
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/* 0x38 SEC i */
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/* 0x39 AND a, y */ op(absolute_y, AND);
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/* 0x3a DEC A */ op(accumulator, DEC);
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@ -519,7 +568,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x44 MVP xyc */ op(block_move, MVP);
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/* 0x45 EOR d */ op(direct, EOR);
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/* 0x46 LSR d */ op(direct_rmw, LSR);
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/* 0x47 EOR [d] */
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/* 0x47 EOR [d] */ op(direct_indirect_long, EOR);
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/* 0x48 PHA s */
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/* 0x49 EOR # */
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/* 0x4a LSR A */ op(accumulator, LSR);
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@ -530,13 +579,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x4f EOR al */ op(absolute_long, EOR);
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/* 0x50 BVC r */
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/* 0x51 EOR (d), y */
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/* 0x51 EOR (d), y */ op(direct_indirect_indexed, EOR);
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/* 0x52 EOR (d) */ op(direct_indirect, EOR);
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/* 0x53 EOR (d, s), y */
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/* 0x54 MVN xyc */ op(block_move, MVN);
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/* 0x55 EOR d, x */
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/* 0x56 LSR d, x */
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/* 0x57 EOR [d],y */
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/* 0x57 EOR [d], y */ op(direct_indirect_indexed_long, EOR);
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/* 0x58 CLI i */
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/* 0x59 EOR a, y */ op(absolute_y, EOR);
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/* 0x5a PHY s */
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@ -553,7 +602,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x64 STZ d */ op(direct, STZ);
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/* 0x65 ADC d */ op(direct, ADC);
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/* 0x66 ROR d */ op(direct_rmw, ROR);
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/* 0x67 ADC [d] */
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/* 0x67 ADC [d] */ op(direct_indirect_long, ADC);
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/* 0x68 PLA s */
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/* 0x69 ADC # */
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/* 0x6a ROR A */ op(accumulator, ROR);
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@ -564,13 +613,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x6f ADC al */ op(absolute_long, ADC);
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/* 0x70 BVS r */
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/* 0x71 ADC (d), y */
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/* 0x71 ADC (d), y */ op(direct_indirect_indexed, ADC);
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/* 0x72 ADC (d) */ op(direct_indirect, ADC);
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/* 0x73 ADC (d, s), y */
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/* 0x74 STZ d, x */
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/* 0x75 ADC d, x */
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/* 0x76 ROR d, x */
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/* 0x77 ADC [d], y */
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/* 0x77 ADC [d], y */ op(direct_indirect_indexed_long, ADC);
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/* 0x78 SEI i */
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/* 0x79 ADC a, y */ op(absolute_y, ADC);
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/* 0x7a PLY s */
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@ -587,7 +636,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x84 STY d */ op(direct, STY);
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/* 0x85 STA d */ op(direct, STA);
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/* 0x86 STX d */ op(direct, STX);
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/* 0x87 STA [d] */
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/* 0x87 STA [d] */ op(direct_indirect_long, STA);
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/* 0x88 DEY i */
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/* 0x89 BIT # */
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/* 0x8a TXA i */
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@ -598,13 +647,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x8f STA al */ op(absolute_long, STA);
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/* 0x90 BCC r */
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/* 0x91 STA (d), y */
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/* 0x91 STA (d), y */ op(direct_indirect_indexed, STA);
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/* 0x92 STA (d) */ op(direct_indirect, STA);
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/* 0x93 STA (d, x), y */
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/* 0x94 STY d, x */
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/* 0x95 STA d, x */
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/* 0x96 STX d, y */
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/* 0x97 STA [d], y */
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/* 0x97 STA [d], y */ op(direct_indirect_indexed_long, STA);
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/* 0x98 TYA i */
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/* 0x99 STA a, y */ op(absolute_y, STA);
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/* 0x9a TXS i */
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@ -621,7 +670,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xa4 LDY d */ op(direct, LDY);
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/* 0xa5 LDA d */ op(direct, LDA);
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/* 0xa6 LDX d */ op(direct, LDX);
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/* 0xa7 LDA [d] */
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/* 0xa7 LDA [d] */ op(direct_indirect_long, LDA);
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/* 0xa8 TAY i */
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/* 0xa9 LDA # */
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/* 0xaa TAX i */
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@ -632,13 +681,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xaf LDA al */ op(absolute_long, LDA);
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/* 0xb0 BCS r */
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/* 0xb1 LDA (d), y */
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/* 0xb1 LDA (d), y */ op(direct_indirect_indexed, LDA);
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/* 0xb2 LDA (d) */ op(direct_indirect, LDA);
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/* 0xb3 LDA (d, s), y */
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/* 0xb4 LDY d, x */
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/* 0xb5 LDA d, x */
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/* 0xb6 LDX d, y */
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/* 0xb7 LDA [d], y */
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/* 0xb7 LDA [d], y */ op(direct_indirect_indexed_long, LDA);
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/* 0xb8 CLV i */
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/* 0xb9 LDA a, y */ op(absolute_y, LDA);
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/* 0xba TSX i */
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@ -655,7 +704,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xc4 CPY d */ op(direct, CPY);
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/* 0xc5 CMP d */ op(direct, CMP);
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/* 0xc6 DEC d */ op(direct_rmw, DEC);
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/* 0xc7 CMP [d] */
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/* 0xc7 CMP [d] */ op(direct_indirect_long, CMP);
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/* 0xc8 INY i */
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/* 0xc9 CMP # */
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/* 0xca DEX i */
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@ -666,13 +715,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xcf CMP al */ op(absolute_long, CMP);
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/* 0xd0 BNE r */
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/* 0xd1 CMP (d), y */
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/* 0xd1 CMP (d), y */ op(direct_indirect_indexed, CMP);
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/* 0xd2 CMP (d) */ op(direct_indirect, CMP);
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/* 0xd3 CMP (d, s), y */
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/* 0xd4 PEI s */
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/* 0xd5 CMP d, x */
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/* 0xd6 DEC d, x */
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/* 0xd7 CMP [d], y */
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/* 0xd7 CMP [d], y */ op(direct_indirect_indexed_long, CMP);
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/* 0xd8 CLD i */
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/* 0xd9 CMP a, y */ op(absolute_y, CMP);
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/* 0xda PHX s */
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@ -689,7 +738,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xe4 CPX d */ op(direct, CPX);
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/* 0xe5 SBC d */ op(direct, SBC);
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/* 0xe6 INC d */ op(direct_rmw, INC);
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/* 0xe7 SBC [d] */
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/* 0xe7 SBC [d] */ op(direct_indirect_long, SBC);
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/* 0xe8 INX i */
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/* 0xe9 SBC # */
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/* 0xea NOP i */
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@ -700,13 +749,13 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xef SBC al */ op(absolute_long, SBC);
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/* 0xf0 BEQ r */
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/* 0xf1 SBC (d), y */
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/* 0xf1 SBC (d), y */ op(direct_indirect_indexed, SBC);
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/* 0xf2 SBC (d) */ op(direct_indirect, SBC);
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/* 0xf3 SBC (d, s), y */
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/* 0xf4 PEA s */
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/* 0xf5 SBC d, x */
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/* 0xf6 INC d, x */
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/* 0xf7 SBC [d], y */
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/* 0xf7 SBC [d], y */ op(direct_indirect_indexed_long, SBC);
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/* 0xf8 SED i */
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/* 0xf9 SBC a, y */ op(absolute_y, SBC);
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/* 0xfa PLX s */
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@ -67,6 +67,9 @@ enum MicroOp: uint8_t {
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// These follow similar skip-one-if-possible logic to OperationConstructDirect.
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OperationConstructDirectIndexedIndirect,
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OperationConstructDirectIndirect,
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OperationConstructDirectIndirectIndexed,
|
||||
OperationConstructDirectIndirectIndexedLong,
|
||||
OperationConstructDirectIndirectLong,
|
||||
|
||||
/// Performs whatever operation goes with this program.
|
||||
OperationPerform,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user