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mirror of https://github.com/TomHarte/CLK.git synced 2024-07-22 15:28:56 +00:00

Ensures the MSX provides a clock to the VDP.

This commit is contained in:
Thomas Harte 2017-11-26 20:07:30 -05:00
parent 9cb6ca3440
commit d33612def5
3 changed files with 17 additions and 4 deletions

View File

@ -23,7 +23,7 @@ std::shared_ptr<Outputs::CRT::CRT> TMS9918::get_crt() {
return crt_; return crt_;
} }
void TMS9918::run_for(const Cycles cycles) { void TMS9918::run_for(const HalfCycles cycles) {
} }
void TMS9918::set_register(int address, uint8_t value) { void TMS9918::set_register(int address, uint8_t value) {

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@ -34,7 +34,7 @@ class TMS9918 {
Runs the VCP for the number of cycles indicate; it is an implicit assumption of the code Runs the VCP for the number of cycles indicate; it is an implicit assumption of the code
that the input clock rate is 3579545 Hz the NTSC colour clock rate. that the input clock rate is 3579545 Hz the NTSC colour clock rate.
*/ */
void run_for(const Cycles cycles); void run_for(const HalfCycles cycles);
void set_register(int address, uint8_t value); void set_register(int address, uint8_t value);
uint8_t get_register(int address); uint8_t get_register(int address);

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@ -84,6 +84,8 @@ class ConcreteMachine:
case CPU::Z80::PartialMachineCycle::Input: case CPU::Z80::PartialMachineCycle::Input:
switch(address & 0xff) { switch(address & 0xff) {
case 0x98: case 0x99: case 0x98: case 0x99:
vdp_->run_for(time_since_vdp_update_);
time_since_vdp_update_ = 0;
*cycle.value = vdp_->get_register(address); *cycle.value = vdp_->get_register(address);
break; break;
@ -102,6 +104,8 @@ class ConcreteMachine:
case CPU::Z80::PartialMachineCycle::Output: case CPU::Z80::PartialMachineCycle::Output:
switch(address & 0xff) { switch(address & 0xff) {
case 0x98: case 0x99: case 0x98: case 0x99:
vdp_->run_for(time_since_vdp_update_);
time_since_vdp_update_ = 0;
vdp_->set_register(address, *cycle.value); vdp_->set_register(address, *cycle.value);
break; break;
@ -127,7 +131,14 @@ class ConcreteMachine:
// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read, // Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
// but otherwise runs without pause. // but otherwise runs without pause.
return HalfCycles((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);; HalfCycles addition((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);
time_since_vdp_update_ += cycle.length + addition;
return addition;
}
void flush() {
vdp_->run_for(time_since_vdp_update_);
time_since_vdp_update_ = 0;
} }
// Obtains the system ROMs. // Obtains the system ROMs.
@ -173,6 +184,8 @@ class ConcreteMachine:
uint8_t ram_[65536]; uint8_t ram_[65536];
uint8_t scratch_[16384]; uint8_t scratch_[16384];
std::vector<uint8_t> basic_, main_; std::vector<uint8_t> basic_, main_;
HalfCycles time_since_vdp_update_;
}; };
} }