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Add timers that count.
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Thomas Harte
parent
ae3cd924e8
commit
d380cecdb7
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@ -153,41 +153,127 @@ struct Video {
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struct Interrupts {
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// TODO: timers, which decrement at 2Mhz.
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void tick_timers() {
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for(int c = 0; c < 4; c++) {
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// Events happen only on a decrement to 0; a reload value of 0 effectively means 'don't count'.
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if(!counters_[c].value && !counters_[c].reload) {
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continue;
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}
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--counters_[c].value;
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if(!counters_[c].value) {
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counters_[c].value = counters_[c].reload;
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// TODO: event triggered here.
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}
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}
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}
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bool read(uint32_t address, uint8_t &value) {
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switch(address & 0x7f) {
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const auto target = address & 0x7f;
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switch(target) {
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default: break;
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case 0x10: // IRQ status A
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value = irq_status_a();
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case 0x00:
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logger.error().append("TODO: IOC control read");
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value = 0;
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return true;
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case 0x20: // IRQ status B
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value = 0x00;
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return true;
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// IRQ A.
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case 0x10: value = irq_a_.status; return true;
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case 0x14: value = irq_a_.request(); return true;
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case 0x18: value = irq_a_.mask; return true;
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case 0x30: // FIQ status
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value = 0x80;
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// IRQ B.
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case 0x20: value = irq_b_.status; return true;
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case 0x24: value = irq_b_.request(); return true;
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case 0x28: value = irq_b_.mask; return true;
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// FIQ.
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case 0x30: value = fiq_.status; return true;
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case 0x34: value = fiq_.request(); return true;
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case 0x38: value = fiq_.mask; return true;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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value = counters_[(target >> 4) - 0x4].output & 0xff;
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return true;
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case 0x44: case 0x54: case 0x64: case 0x74:
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value = counters_[(target >> 4) - 0x4].output >> 8;
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return true;
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}
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logger.error().append("TODO: IO controller read from %08x", address);
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logger.error().append("TODO: IO controller read from %08x", address);
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return false;
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}
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bool write(uint32_t address, uint8_t value) {
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const auto target = address & 0x7f;
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switch(target) {
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default: break;
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case 0x00:
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logger.error().append("TODO: IOC control write %02x", value);
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return true;
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case 0x14:
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logger.error().append("TODO: IRQ clear write %02x", value);
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// b2: clear IF.
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// b3: clear IR.
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// b4: clear POR.
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// b5: clear TM[0].
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// b6: clear TM[1].
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return true;
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// Interrupts.
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case 0x18: irq_a_.mask = value; return true;
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case 0x28: irq_b_.mask = value; return true;
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case 0x38: fiq_.mask = value; return true;
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// Counters.
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case 0x40: case 0x50: case 0x60: case 0x70:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0xff00) | value
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);
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return true;
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case 0x44: case 0x54: case 0x64: case 0x74:
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counters_[(target >> 4) - 0x4].reload = uint16_t(
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(counters_[(target >> 4) - 0x4].reload & 0x00ff) | (value << 8)
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);
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return true;
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case 0x48: case 0x58: case 0x68: case 0x78:
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counters_[(target >> 4) - 0x4].value = counters_[(target >> 4) - 0x4].reload;
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return true;
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case 0x4c: case 0x5c: case 0x6c: case 0x7c:
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counters_[(target >> 4) - 0x4].output = counters_[(target >> 4) - 0x4].value;
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return true;
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}
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logger.error().append("TODO: IO controller write of %02x at %08x", value, address);
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return false;
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}
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private:
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uint8_t irq_status_a() const {
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return irq_status_a_;
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Interrupts() {
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irq_a_.status = 0x80 | 0x10; // i.e. 'set always' + 'power-on'.
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irq_b_.status = 0x00;
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fiq_.status = 0x80; // 'set always'.
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}
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uint8_t irq_status_a_ = 0x80 | 0x10; // 0x80 = always; 0x10 = at power-on.
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private:
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struct Interrupt {
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uint8_t status, mask;
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uint8_t request() const {
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return status & mask;
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}
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};
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Interrupt irq_a_, irq_b_, fiq_;
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struct Counter {
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uint16_t value;
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uint16_t reload;
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uint16_t output;
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};
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Counter counters_[4];
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};
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/// Primarily models the MEMC.
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@ -242,7 +328,9 @@ struct Memory {
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return true;
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} break;
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case Zone::IOControllers: return ioc_.write(address, source);
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case Zone::IOControllers:
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ioc_.write(address, source);
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return true;
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case Zone::VideoController:
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// TODO: handle byte writes correctly.
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@ -305,13 +393,15 @@ struct Memory {
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case Zone::IOControllers: {
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if constexpr (std::is_same_v<IntT, uint8_t>) {
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return ioc_.read(address, source);
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ioc_.read(address, source);
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return true;
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} else {
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// TODO: generalise this adaptation of an 8-bit device to the 32-bit bus, which probably isn't right anyway.
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uint8_t value;
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if(!ioc_.read(address, value)) {
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return false;
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}
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ioc_.read(address, value);
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// if(!ioc_.read(address, value)) {
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// return false;
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// }
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source = value;
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return true;
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}
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@ -610,10 +700,10 @@ class ConcreteMachine:
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}
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// TODO: pipeline prefetch?
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// static bool log = false;
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// if(log) {
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// logger.info().append("%08x: %08x [r14:%08x]", executor_.pc(), instruction, executor_.registers()[14]);
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// }
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static bool log = false;
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if(log) {
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logger.info().append("%08x: %08x [r14:%08x]", executor_.pc(), instruction, executor_.registers()[14]);
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}
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InstructionSet::ARM::execute<arm_model>(instruction, executor_);
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}
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