6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into OptionalWait

Browse Source
This commit is contained in:
Thomas Harte 2017-08-26 23:11:23 -04:00
commit d411827733
1 changed files with 15 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
Components/6845/CRTC6845.hpp
View File

@ -75,8 +75,9 @@ template <class T> class CRTC6845 {
0xff, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff 0xff, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff
}; };
if(selected_register_ < 16) if(selected_register_ < 16) {
registers_[selected_register_] = value & masks[selected_register_]; registers_[selected_register_] = value & masks[selected_register_];
}
} }
void trigger_light_pen() { void trigger_light_pen() {
@ -87,19 +88,6 @@ template <class T> class CRTC6845 {
void run_for(Cycles cycles) { void run_for(Cycles cycles) {
int cyles_remaining = cycles.as_int(); int cyles_remaining = cycles.as_int();
while(cyles_remaining--) { while(cyles_remaining--) {
// check for start of horizontal sync
if(character_counter_ == registers_[2]) {
hsync_counter_ = 0;
bus_state_.hsync = true;
}
// check for end of horizontal sync; note that a sync time of zero will result in an immediate
// cancellation of the plan to perform sync
if(bus_state_.hsync) {
bus_state_.hsync = hsync_counter_ != (registers_[3] & 15);
hsync_counter_ = (hsync_counter_ + 1) & 15;
}
// check for end of visible characters // check for end of visible characters
if(character_counter_ == registers_[1]) { if(character_counter_ == registers_[1]) {
// TODO: consider skew in character_is_visible_. Or maybe defer until perform_bus_cycle? // TODO: consider skew in character_is_visible_. Or maybe defer until perform_bus_cycle?
@ -120,6 +108,19 @@ template <class T> class CRTC6845 {
character_counter_++; character_counter_++;
} }
// check for start of horizontal sync
if(character_counter_ == registers_[2]) {
hsync_counter_ = 0;
bus_state_.hsync = true;
}
// check for end of horizontal sync; note that a sync time of zero will result in an immediate
// cancellation of the plan to perform sync
if(bus_state_.hsync) {
bus_state_.hsync = hsync_counter_ != (registers_[3] & 15);
hsync_counter_ = (hsync_counter_ + 1) & 15;
}
perform_bus_cycle_phase2(); perform_bus_cycle_phase2();
} }
} }