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https://github.com/TomHarte/CLK.git
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Introduce directional ADD/SUB/AND/OR.
Just 512 failures to go.
This commit is contained in:
Thomas Harte
parent
72772c9a83
commit
d4b766bf3f
@ -93,6 +93,22 @@ constexpr Operation Predecoder<model>::operation(OpT op) {
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#undef ImmediateGroup
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case ADDtoRb: case ADDtoMb: return Operation::ADDb;
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case ADDtoRw: case ADDtoMw: return Operation::ADDw;
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case ADDtoRl: case ADDtoMl: return Operation::ADDl;
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case SUBtoRb: case SUBtoMb: return Operation::SUBb;
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case SUBtoRw: case SUBtoMw: return Operation::SUBw;
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case SUBtoRl: case SUBtoMl: return Operation::SUBl;
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case ANDtoRb: case ANDtoMb: return Operation::ANDb;
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case ANDtoRw: case ANDtoMw: return Operation::ANDw;
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case ANDtoRl: case ANDtoMl: return Operation::ANDl;
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case ORtoRb: case ORtoMb: return Operation::ORb;
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case ORtoRw: case ORtoMw: return Operation::ORw;
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case ORtoRl: case ORtoMl: return Operation::ORl;
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default: break;
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}
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@ -171,9 +187,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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}
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// ADD, SUB, MOVE, MOVEA
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case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl):
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case ADDQb: case ADDQw: case ADDQl:
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case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
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case SUBQb: case SUBQw: case SUBQl:
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case OpT(Operation::MOVEb): case OpT(Operation::MOVEw): case OpT(Operation::MOVEl):
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case OpT(Operation::MOVEAw): case OpT(Operation::MOVEAl):
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@ -182,9 +196,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
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// TODO: I'm going to need get-size-by-operation elsewhere; use that here when implemented.
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constexpr bool is_byte =
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op == OpT(Operation::ADDb) || op == OpT(Operation::SUBb) || op == OpT(Operation::MOVEb) ||
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op == ADDQb || op == SUBQb || op == OpT(Operation::ANDb) || op == OpT(Operation::EORb) ||
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op == OpT(Operation::ORb);
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op == OpT(Operation::MOVEb) || op == ADDQb || op == SUBQb || op == OpT(Operation::EORb);
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switch(original.mode<0>()) {
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default: break;
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@ -213,6 +225,63 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
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}
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}
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case ANDtoRb: case ANDtoRw: case ANDtoRl:
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case ORtoRb: case ORtoRw: case ORtoRl:
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case SUBtoRb: case SUBtoRw: case SUBtoRl:
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case ADDtoRb: case ADDtoRw: case ADDtoRl: {
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constexpr bool is_byte = op == ADDtoRb || op == SUBtoRb || op == SUBtoRb || op == ADDtoRb;
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switch(original.mode<0>()) {
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default: return original;
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case AddressingMode::AddressRegisterDirect:
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if constexpr (!is_byte) {
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return original;
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}
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[[fallthrough]];
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case AddressingMode::None:
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return Preinstruction();
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}
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}
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case ADDtoMb: case ADDtoMw: case ADDtoMl:
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case SUBtoMb: case SUBtoMw: case SUBtoMl:
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case ANDtoMb: case ANDtoMw: case ANDtoMl:
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case ORtoMb: case ORtoMw: case ORtoMl: {
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// TODO: I'm going to need get-size-by-operation elsewhere; use that here when implemented.
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constexpr bool is_byte = op == ADDtoMb || op == SUBtoMb || op == ANDtoMb || op == ORtoMb;
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switch(original.mode<0>()) {
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default: break;
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case AddressingMode::AddressRegisterDirect:
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if constexpr (!is_byte) {
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break;
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}
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[[fallthrough]];
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case AddressingMode::None:
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return Preinstruction();
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}
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switch(original.mode<1>()) {
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default: return original;
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case AddressingMode::DataRegisterDirect:
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// TODO: this is per the documentation, but is it true?
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if constexpr (op == ANDtoMb || op == ANDtoMw || op == ANDtoMl || op == ORtoMb || op == ORtoMw || op == ORtoMl) {
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return Preinstruction();
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}
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case AddressingMode::AddressRegisterDirect:
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if constexpr (!is_byte) {
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return original;
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}
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[[fallthrough]];
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case AddressingMode::ImmediateData:
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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case AddressingMode::None:
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return Preinstruction();
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}
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}
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case OpT(Operation::NOTb): case OpT(Operation::NOTw): case OpT(Operation::NOTl):
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switch(original.mode<0>()) {
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default: return original;
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@ -461,7 +530,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// b0–b2 and b3–b5: an effective address;
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// b6–b8: an opmode, i.e. source + direction.
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//
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case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl):
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case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
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case OpT(Operation::ANDb): case OpT(Operation::ANDw): case OpT(Operation::ANDl):
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case OpT(Operation::ORb): case OpT(Operation::ORw): case OpT(Operation::ORl): {
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@ -470,14 +538,14 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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// TODO: make this decision outside of this function.
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if(opmode & 4) {
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// Dn Λ < ea > → < ea >
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// Dn, <ea>
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return validated<op, validate>(
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Preinstruction(operation,
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AddressingMode::DataRegisterDirect, data_register,
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ea_combined_mode, ea_register));
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} else {
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// < ea > Λ Dn → Dn
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// <ea>, Dn
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return validated<op, validate>(
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Preinstruction(operation,
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@ -488,12 +556,21 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::decode(ui
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return Preinstruction();
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}
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case ADDtoRb: case ADDtoRw: case ADDtoRl:
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case SUBtoRb: case SUBtoRw: case SUBtoRl:
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case ANDtoRb: case ANDtoRw: case ANDtoRl:
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case ORtoRb: case ORtoRw: case ORtoRl:
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case OpT(Operation::CMPb): case OpT(Operation::CMPw): case OpT(Operation::CMPl):
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return validated<op, validate>(
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Preinstruction(operation,
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combined_mode(ea_mode, ea_register), ea_register,
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AddressingMode::DataRegisterDirect, data_register));
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case ADDtoMb: case ADDtoMw: case ADDtoMl:
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case SUBtoMb: case SUBtoMw: case SUBtoMl:
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case ANDtoMb: case ANDtoMw: case ANDtoMl:
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case ORtoMb: case ORtoMw: case ORtoMl:
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case OpT(Operation::EORb): case OpT(Operation::EORw): case OpT(Operation::EORl):
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return validated<op, validate>(
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Preinstruction(operation,
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@ -1136,17 +1213,18 @@ Preinstruction Predecoder<model>::decode8(uint16_t instruction) {
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// 4-171 (p275)
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if((instruction & 0x1f0) == 0x100) Decode(Op::SBCD);
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// 4-150 (p254)
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switch(instruction & 0x0c0) {
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case 0x00: Decode(Op::ORb);
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case 0x40: Decode(Op::ORw);
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case 0x80: Decode(Op::ORl);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x0c0: Decode(Op::DIVU); // 4-97 (p201)
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case 0x1c0: Decode(Op::DIVS); // 4-93 (p197)
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// 4-150 (p254)
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case 0x000: Decode(ORtoRb);
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case 0x040: Decode(ORtoRw);
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case 0x080: Decode(ORtoRl);
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case 0x100: Decode(ORtoMb);
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case 0x140: Decode(ORtoMw);
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case 0x180: Decode(ORtoMl);
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default: break;
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}
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@ -1171,14 +1249,13 @@ Preinstruction Predecoder<model>::decode9(uint16_t instruction) {
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case 0x0c0: Decode(Op::SUBAw);
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case 0x1c0: Decode(Op::SUBAl);
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default: break;
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}
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switch(instruction & 0x0c0) {
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// 4-174 (p278)
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case 0x00: Decode(Op::SUBb);
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case 0x40: Decode(Op::SUBw);
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case 0x80: Decode(Op::SUBl);
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case 0x000: Decode(SUBtoRb);
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case 0x040: Decode(SUBtoRw);
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case 0x080: Decode(SUBtoRl);
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case 0x100: Decode(SUBtoMb);
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case 0x140: Decode(SUBtoMw);
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case 0x180: Decode(SUBtoMl);
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default: break;
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}
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@ -1245,18 +1322,18 @@ Preinstruction Predecoder<model>::decodeC(uint16_t instruction) {
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switch(instruction & 0x1c0) {
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case 0x0c0: Decode(Op::MULU); // 4-139 (p243)
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case 0x1c0: Decode(Op::MULS); // 4-136 (p240)
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default: break;
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}
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switch(instruction & 0x0c0) {
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// 4-15 (p119)
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case 0x00: Decode(Op::ANDb);
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case 0x40: Decode(Op::ANDw);
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case 0x80: Decode(Op::ANDl);
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case 0x000: Decode(ANDtoRb);
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case 0x040: Decode(ANDtoRw);
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case 0x080: Decode(ANDtoRl);
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case 0x100: Decode(ANDtoMb);
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case 0x140: Decode(ANDtoMw);
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case 0x180: Decode(ANDtoMl);
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default: break;
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}
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return Preinstruction();
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}
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@ -1278,14 +1355,13 @@ Preinstruction Predecoder<model>::decodeD(uint16_t instruction) {
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case 0x0c0: Decode(Op::ADDAw);
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case 0x1c0: Decode(Op::ADDAl);
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default: break;
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}
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switch(instruction & 0x0c0) {
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// 4-4 (p108)
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case 0x000: Decode(Op::ADDb);
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case 0x040: Decode(Op::ADDw);
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case 0x080: Decode(Op::ADDl);
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case 0x000: Decode(ADDtoRb);
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case 0x040: Decode(ADDtoRw);
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case 0x080: Decode(ADDtoRl);
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case 0x100: Decode(ADDtoMb);
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case 0x140: Decode(ADDtoMw);
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case 0x180: Decode(ADDtoMl);
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default: break;
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}
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@ -78,6 +78,18 @@ template <Model model> class Predecoder {
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CMPMb, CMPMw, CMPMl,
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MOVEq,
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ADDtoMb, ADDtoMw, ADDtoMl,
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ADDtoRb, ADDtoRw, ADDtoRl,
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SUBtoMb, SUBtoMw, SUBtoMl,
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SUBtoRb, SUBtoRw, SUBtoRl,
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ANDtoMb, ANDtoMw, ANDtoMl,
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ANDtoRb, ANDtoRw, ANDtoRl,
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ORtoMb, ORtoMw, ORtoMl,
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ORtoRb, ORtoRw, ORtoRl,
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};
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static constexpr Operation operation(OpT op);
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@ -225,9 +225,9 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
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case Operation::MOVEPl: instruction = @"MOVEP.l"; break;
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case Operation::MOVEPw: instruction = @"MOVEP.w"; break;
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// case Operation::ANDb: instruction = @"AND.b"; break;
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// case Operation::ANDw: instruction = @"AND.w"; break;
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// case Operation::ANDl: instruction = @"AND.l"; break;
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case Operation::ANDb: instruction = @"AND.b"; break;
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case Operation::ANDw: instruction = @"AND.w"; break;
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case Operation::ANDl: instruction = @"AND.l"; break;
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case Operation::EORb: instruction = @"EOR.b"; break;
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case Operation::EORw: instruction = @"EOR.w"; break;
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@ -237,9 +237,9 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
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case Operation::NOTw: instruction = @"NOT.w"; break;
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case Operation::NOTl: instruction = @"NOT.l"; break;
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// case Operation::ORb: instruction = @"OR.b"; break;
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// case Operation::ORw: instruction = @"OR.w"; break;
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// case Operation::ORl: instruction = @"OR.l"; break;
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case Operation::ORb: instruction = @"OR.b"; break;
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case Operation::ORw: instruction = @"OR.w"; break;
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case Operation::ORl: instruction = @"OR.l"; break;
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case Operation::MULU: instruction = @"MULU"; break;
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case Operation::MULS: instruction = @"MULS"; break;
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