diff --git a/Components/9918/Implementation/Storage.hpp b/Components/9918/Implementation/Storage.hpp
index 1d3389781..c1260eb99 100644
--- a/Components/9918/Implementation/Storage.hpp
+++ b/Components/9918/Implementation/Storage.hpp
@@ -59,7 +59,7 @@ struct YamahaFetcher {
 				type(type),
 				id(id) {}
 
-			constexpr Event() noexcept {}
+			constexpr Event() noexcept = default;
 		};
 
 		// State that tracks fetching position within a line.
diff --git a/InstructionSets/x86/Instruction.hpp b/InstructionSets/x86/Instruction.hpp
index a1e475152..10d1f18f4 100644
--- a/InstructionSets/x86/Instruction.hpp
+++ b/InstructionSets/x86/Instruction.hpp
@@ -564,7 +564,7 @@ constexpr Operation rep_operation(Operation operation, Repetition repetition) {
 /// It cannot natively describe a base of ::None.
 class ScaleIndexBase {
 	public:
-		constexpr ScaleIndexBase() noexcept {}
+		constexpr ScaleIndexBase() noexcept = default;
 		constexpr ScaleIndexBase(uint8_t sib) noexcept : sib_(sib) {}
 		constexpr ScaleIndexBase(int scale, Source index, Source base) noexcept :
 			sib_(uint8_t(
@@ -703,7 +703,7 @@ template<bool is_32bit> class Instruction {
 		using ImmediateT = typename std::conditional<is_32bit, uint32_t, uint16_t>::type;
 		using AddressT = ImmediateT;
 
-		constexpr Instruction() noexcept {}
+		constexpr Instruction() noexcept = default;
 		constexpr Instruction(Operation operation) noexcept :
 			Instruction(operation, Source::None, Source::None, ScaleIndexBase(), false, AddressSize::b16, Source::None, DataSize::None, 0, 0) {}
 		constexpr Instruction(
diff --git a/Outputs/ScanTargets/BufferingScanTarget.hpp b/Outputs/ScanTargets/BufferingScanTarget.hpp
index 896aa8286..9d43c22c7 100644
--- a/Outputs/ScanTargets/BufferingScanTarget.hpp
+++ b/Outputs/ScanTargets/BufferingScanTarget.hpp
@@ -203,7 +203,7 @@ class BufferingScanTarget: public Outputs::Display::ScanTarget {
 		struct PointerSet {
 			// This constructor is here to appease GCC's interpretation of
 			// an ambiguity in the C++ standard; cf. https://stackoverflow.com/questions/17430377
-			PointerSet() noexcept {}
+			PointerSet() noexcept = default;
 
 			// Squeezing this struct into 64 bits makes the std::atomics more likely
 			// to be lock free; they are under LLVM x86-64.
diff --git a/Processors/68000/68000.hpp b/Processors/68000/68000.hpp
index 0b271292b..013d36145 100644
--- a/Processors/68000/68000.hpp
+++ b/Processors/68000/68000.hpp
@@ -145,7 +145,7 @@ struct Microcycle: public MicrocycleOperationStorage<op> {
 	*/
 	SlicedInt16 *value = nullptr;
 
-	constexpr Microcycle() noexcept {}
+	constexpr Microcycle() noexcept = default;
 	constexpr Microcycle(OperationT dynamic_operation) noexcept {
 		if constexpr (op == Operation::DecodeDynamically) {
 			MicrocycleOperationStorage<op>::operation = dynamic_operation;
diff --git a/Storage/Disk/Encodings/MFM/Sector.hpp b/Storage/Disk/Encodings/MFM/Sector.hpp
index 646b7d3ea..d07d05777 100644
--- a/Storage/Disk/Encodings/MFM/Sector.hpp
+++ b/Storage/Disk/Encodings/MFM/Sector.hpp
@@ -40,7 +40,7 @@ struct Sector {
 	bool has_header_crc_error = false;
 	bool is_deleted = false;
 
-	Sector() noexcept {}
+	Sector() noexcept = default;
 
 	Sector(const Sector &&rhs) noexcept :
 		address(rhs.address),