6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-02-23 03:29:04 +00:00
Code Issues Projects Releases Wiki Activity

Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.

Browse Source
This commit is contained in:
Thomas Harte 2019-03-22 23:27:48 -04:00
parent ed7060a105
commit d7c3d4ce52
3 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
OSBindings/Mac/Clock SignalTests/68000Tests.mm
View File

@ -124,7 +124,9 @@ class RAM68000: public CPU::MC68000::BusHandler {
_machine->set_program({ _machine->set_program({
0x303c, 0xfb2e, // MOVE #fb2e, D0 0x303c, 0xfb2e, // MOVE #fb2e, D0
0x3200, // MOVE D0, D1 0x3200, // MOVE D0, D1
0x3040, // MOVE D0, A0
0x3040, // MOVEA D0, A0
0x3278, 0x0400, // MOVEA.w (0x0400), A1
}); });
// Perform RESET. // Perform RESET.
@ -142,10 +144,15 @@ class RAM68000: public CPU::MC68000::BusHandler {
state = _machine->get_processor_state(); state = _machine->get_processor_state();
XCTAssert(state.data[1] == 0xfb2e); XCTAssert(state.data[1] == 0xfb2e);
// Perform MOVE D0, A0 // Perform MOVEA D0, A0
_machine->run_for(Cycles(4)); _machine->run_for(Cycles(4));
state = _machine->get_processor_state(); state = _machine->get_processor_state();
XCTAssert(state.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.address[0]); XCTAssert(state.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.address[0]);
// Perform MOVEA.w (0x1000), A1
_machine->run_for(Cycles(13));
state = _machine->get_processor_state();
XCTAssert(state.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.address[1]);
} }
@end @end

5
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -239,11 +239,12 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
#undef CalculateD8AnXn #undef CalculateD8AnXn
case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask: case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask:
effective_address_[0] = prefetch_queue_.halves.high.full; // Assumption: this will be assembling right at the start of the instruction.
effective_address_[0] = prefetch_queue_.halves.low.full;
break; break;
case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask: case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask:
effective_address_[1] = prefetch_queue_.halves.high.full; effective_address_[1] = prefetch_queue_.halves.low.full;
break; break;
case int(MicroOp::Action::AssembleLongWordFromPrefetch) | MicroOp::SourceMask: case int(MicroOp::Action::AssembleLongWordFromPrefetch) | MicroOp::SourceMask:

20
Processors/68000/Implementation/68000Storage.cpp
View File

@ -387,14 +387,14 @@ struct ProcessorStorageConstructor {
} else { } else {
op(); op();
} }
continue; break;
case 0x0004: // MOVE Dn, -(An) case 0x0004: // MOVE Dn, -(An)
case 0x0104: // MOVE An, -(An) case 0x0104: // MOVE An, -(An)
op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask, op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
seq("np nw", { &storage_.address_[destination_register].full }, !is_byte_access)); seq("np nw", { &storage_.address_[destination_register].full }, !is_byte_access));
op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw); op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
continue; break;
case 0x0005: // MOVE Dn, (d16, An) case 0x0005: // MOVE Dn, (d16, An)
case 0x0105: // MOVE An, (d16, An) case 0x0105: // MOVE An, (d16, An)
@ -562,12 +562,14 @@ struct ProcessorStorageConstructor {
// Source = (xxx).W // Source = (xxx).W
// //
case 0x1001: // MOVEA (xxx).W, Dn case 0x1001: // MOVEA (xxx).W, An
operation = Operation::MOVEAw; operation = Operation::MOVEAw;
case 0x1000: // MOVE (xxx).W, Dn case 0x1000: // MOVE (xxx).W, Dn
op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np")); op(
op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access)); int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask,
continue; seq("np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
op(Action::PerformOperation);
break;
case 0x1002: // MOVE (xxx).W, (An) case 0x1002: // MOVE (xxx).W, (An)
case 0x1003: // MOVE (xxx).W, (An)+ case 0x1003: // MOVE (xxx).W, (An)+
@ -603,7 +605,8 @@ struct ProcessorStorageConstructor {
case 0x1100: // MOVE (xxx).W, Dn case 0x1100: // MOVE (xxx).W, Dn
op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np np")); op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access)); op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access));
continue; op();
break;
// //
// Source = (d16, PC) // Source = (d16, PC)
@ -640,11 +643,10 @@ struct ProcessorStorageConstructor {
// //
default: default:
std::cerr << "Unimplemented MOVE " << std::hex << both_modes << std::endl; std::cerr << "Unimplemented MOVE " << std::hex << both_modes << " " << instruction << std::endl;
// TODO: all other types of mode. // TODO: all other types of mode.
continue; continue;
} }
} }
} break; } break;