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https://github.com/TomHarte/CLK.git
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Test loads and stores, and immediate arithmetic.
This commit is contained in:
parent
2d69896f64
commit
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@ -63,8 +63,10 @@ enum class BranchOption: uint32_t {
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enum class Operation: uint8_t {
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enum class Operation: uint8_t {
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Undefined,
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Undefined,
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//
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// These 601-exclusive instructions; a lot of them are carry-overs
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// These 601-exclusive instructions; a lot of them are carry-overs
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// from POWER. These are not part of the PowerPC architecture.
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// from POWER. These are not part of the PowerPC architecture.
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//
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/// |rA| is placed into rD. If rA = 0x8000'0000 then 0x8000'0000 is placed into rD
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/// |rA| is placed into rD. If rA = 0x8000'0000 then 0x8000'0000 is placed into rD
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/// and XER[OV] is set if oe() indicates that overflow is enabled.
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/// and XER[OV] is set if oe() indicates that overflow is enabled.
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@ -100,8 +102,35 @@ enum class Operation: uint8_t {
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nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
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nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
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sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
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sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
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//
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// 32- and 64-bit PowerPC instructions.
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// 32- and 64-bit PowerPC instructions.
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addx, addcx, addex, addi, addic, addic_, addis, addmex, addzex, andx,
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//
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addx, addcx, addex,
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/// Add immediate.
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///
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/// rD() = (rA() | 0) + simm()
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addi,
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/// Add immediate carrying.
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] = carry.
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addic,
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/// Add immediate carrying.
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] = carry, and the condition register is updated.
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addic_,
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/// Add immediate shifter.
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///
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/// rD() = (rA() | 0) + (simm() << 16)
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addis,
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addmex, addzex, andx,
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andcx, andi_, andis_,
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andcx, andi_, andis_,
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/// Branch unconditional.
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/// Branch unconditional.
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@ -169,7 +198,45 @@ enum class Operation: uint8_t {
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lbzx,
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lbzx,
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lfd, lfdu, lfdux, lfdx, lfs, lfsu,
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lfd, lfdu, lfdux, lfdx, lfs, lfsu,
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lfsux, lfsx, lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, lmw,
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lfsux, lfsx, lha, lhau,
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/// Load half-word algebraic with update indexed.
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///
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/// rD()[16, 31] = [ rA()|0 + rB() ]; and rA() is set to the calculated address
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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/// The result in rD is sign extended.
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///
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/// PowerPC defines rA=0 and rA=rD to be invalid forms; the MPC601
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/// will suppress the update if rA=0 or rA=rD.
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lhaux,
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/// Load half-word algebraic indexed.
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///
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/// rD[16, 31] = [ (rA()|0) + rB() ]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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/// The result in rD is sign extended.
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lhax,
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lhbrx, lhz, lhzu,
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/// Load half-word and zero with update indexed.
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///
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/// rD()[16, 31] = [ rA()|0 + rB() ]; and rA() is set to the calculated address
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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/// The rest of rD is set to 0.
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///
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/// PowerPC defines rA=0 and rA=rD to be invalid forms; the MPC601
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/// will suppress the update if rA=0 or rA=rD.
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lhzux,
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/// Load half-word and zero indexed.
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///
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/// rD[16, 31] = [ (rA()|0) + rB() ]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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/// The rest of rD is set to 0.
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lhzx,
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lmw,
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lswi, lswx, lwarx, lwbrx, lwz, lwzu,
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lswi, lswx, lwarx, lwbrx, lwz, lwzu,
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/// Load word and zero with update indexed.
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/// Load word and zero with update indexed.
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@ -189,12 +256,74 @@ enum class Operation: uint8_t {
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mcrf, mcrfs, mcrxr,
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mcrf, mcrfs, mcrxr,
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mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
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mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
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mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux, mulli, mullwx,
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mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux,
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/// Multiply low immediate.
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///
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/// rD() = [low 32 bits of] rA() * simm()
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/// XER[OV] is set if, were the operands treated as signed, overflow occurred.
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mulli,
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mullwx,
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nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,
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nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,
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sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu,
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sc, slwx, srawx, srawix, srwx, stb, stbu,
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stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx,
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stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx,
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/// Store byte with update indexed.
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subfex, subfic, subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
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///
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/// [ (ra()|0) + rB() ] = rS()[24, 31]; and rA() is updated with the calculated address.
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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///
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/// PowerPC defines rA=0 to an invalid form; the MPC601 will store to r0.
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stbux,
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/// Store byte indexed.
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///
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/// [ (ra()|0) + rB() ] = rS()[24, 31]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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stbx,
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stfd, stfdu,
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stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu,
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/// Store half-word with update indexed.
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///
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/// [ (ra()|0) + rB() ] = rS()[16, 31]; and rA() is updated with the calculated address.
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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///
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/// PowerPC defines rA=0 to an invalid form; the MPC601 will store to r0.
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sthux,
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/// Store half-word indexed.
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///
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/// [ (ra()|0) + rB() ] = rS()[16, 31]
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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sthx,
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stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu,
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/// Store word with update indexed.
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///
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/// [ (ra()|0) + rB() ] = rS(); and rA() is updated with the calculated address.
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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///
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/// PowerPC defines rA=0 to an invalid form; the MPC601 will store to r0.
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stwux,
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/// Store word indexed.
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///
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/// [ (ra()|0) + rB() ] = rS()
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/// i.e. if rA() is 0 then the value 0 is used, not the contents of r0.
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stwx,
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subfx, subfcx,
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subfex,
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/// Subtract from immediate carrying
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///
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/// rD() = ~rA() + simm() + 1
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subfic,
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subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
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// 32-bit, supervisor level.
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// 32-bit, supervisor level.
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dcbi,
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dcbi,
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@ -205,7 +334,9 @@ enum class Operation: uint8_t {
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// Optional.
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// Optional.
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fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
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fresx, frsqrtex, fselx, fsqrtx, slbia, slbie, stfiwx,
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//
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// 64-bit only PowerPC instructions.
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// 64-bit only PowerPC instructions.
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//
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux,
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ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
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ldx, sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux,
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sradix, srdx, sradx, extsw, fsqrtsx, std, stdu, stdcx_,
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sradix, srdx, sradx, extsw, fsqrtsx, std, stdu, stdcx_,
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@ -17,6 +17,16 @@ using namespace InstructionSet::PowerPC;
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@interface DingusdevPowerPCTests : XCTestCase
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@interface DingusdevPowerPCTests : XCTestCase
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@end
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@end
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namespace {
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void AssertEqualOperationName(NSString *lhs, NSString *rhs) {
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NSString *const lhsMapped = [lhs stringByReplacingOccurrencesOfString:@"_" withString:@"."];
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NSString *const rhsMapped = [rhs stringByReplacingOccurrencesOfString:@"_" withString:@"."];
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XCTAssertEqualObjects(lhsMapped, rhsMapped);
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}
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}
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@implementation DingusdevPowerPCTests
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@implementation DingusdevPowerPCTests
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- (void)testABDInstruction:(Instruction)instruction columns:(NSArray<NSString *> *)columns testZero:(BOOL)testZero {
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- (void)testABDInstruction:(Instruction)instruction columns:(NSArray<NSString *> *)columns testZero:(BOOL)testZero {
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@ -57,21 +67,52 @@ using namespace InstructionSet::PowerPC;
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NSString *const operation = columns[2];
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NSString *const operation = columns[2];
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const auto instruction = decoder.decode(opcode);
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const auto instruction = decoder.decode(opcode);
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NSLog(@"%@", line);
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switch(instruction.operation) {
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switch(instruction.operation) {
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default:
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default:
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NSAssert(FALSE, @"Didn't handle %@", line);
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NSAssert(FALSE, @"Didn't handle %@", line);
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break;
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break;
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#define ArithImm(x) \
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case Operation::x: { \
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NSString *const rD = [NSString stringWithFormat:@"r%d", instruction.rD()]; \
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NSString *const rA = [NSString stringWithFormat:@"r%d", instruction.rA()]; \
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const auto simm = strtol([columns[5] UTF8String], NULL, 16); \
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AssertEqualOperationName(operation, @#x); \
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XCTAssertEqualObjects(columns[3], rD); \
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XCTAssertEqualObjects(columns[4], rA); \
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XCTAssertEqual(simm, instruction.simm()); \
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} break;
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ArithImm(mulli);
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ArithImm(subfic);
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ArithImm(addi);
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ArithImm(addic);
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ArithImm(addic_);
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ArithImm(addis);
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#undef ArithImm
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#define ABCz(x) \
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#define ABCz(x) \
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case Operation::x: \
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case Operation::x: \
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XCTAssertEqualObjects(operation, @#x); \
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AssertEqualOperationName(operation, @#x); \
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[self testABDInstruction:instruction columns:columns testZero:YES]; \
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[self testABDInstruction:instruction columns:columns testZero:YES]; \
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break;
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break;
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ABCz(lwzux);
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ABCz(lwzx);
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ABCz(lwzx);
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ABCz(lwzux);
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ABCz(lbzx);
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ABCz(lbzx);
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ABCz(lbzux);
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ABCz(lbzux);
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ABCz(stwx);
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ABCz(stwux);
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ABCz(stbx);
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ABCz(stbux);
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ABCz(lhzx);
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ABCz(lhzux);
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ABCz(lhax);
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ABCz(lhaux);
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ABCz(sthx);
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ABCz(sthux);
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#undef ABCz
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#undef ABCz
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@ -164,7 +205,7 @@ using namespace InstructionSet::PowerPC;
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if(instruction.branch_prediction_hint()) {
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if(instruction.branch_prediction_hint()) {
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baseOperation = [baseOperation stringByAppendingString:@"+"];
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baseOperation = [baseOperation stringByAppendingString:@"+"];
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}
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}
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XCTAssertEqualObjects(operation, baseOperation);
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AssertEqualOperationName(operation, baseOperation);
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}
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}
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if(instruction.bi() & ~3) {
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if(instruction.bi() & ~3) {
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@ -190,10 +231,10 @@ using namespace InstructionSet::PowerPC;
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case Operation::bx: {
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case Operation::bx: {
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switch((instruction.aa() ? 2 : 0) | (instruction.lk() ? 1 : 0)) {
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switch((instruction.aa() ? 2 : 0) | (instruction.lk() ? 1 : 0)) {
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case 0: XCTAssertEqualObjects(operation, @"b"); break;
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case 0: AssertEqualOperationName(operation, @"b"); break;
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case 1: XCTAssertEqualObjects(operation, @"bl"); break;
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case 1: AssertEqualOperationName(operation, @"bl"); break;
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case 2: XCTAssertEqualObjects(operation, @"ba"); break;
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case 2: AssertEqualOperationName(operation, @"ba"); break;
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case 3: XCTAssertEqualObjects(operation, @"bla"); break;
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case 3: AssertEqualOperationName(operation, @"bla"); break;
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}
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}
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const uint32_t destination = uint32_t(std::strtol([columns[3] UTF8String], 0, 16));
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const uint32_t destination = uint32_t(std::strtol([columns[3] UTF8String], 0, 16));
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