6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-12 00:30:31 +00:00
Code Issues Projects Releases Wiki Activity

Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207.

Browse Source 
Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.
This commit is contained in:
Thomas Harte 2017-06-11 13:32:20 -04:00
parent db30f53ab0
commit d910a4fd38
2 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Machines/ZX8081/Video.cpp
View File

@ -11,7 +11,7 @@
using namespace ZX8081;
Video::Video() :
crt_(new Outputs::CRT::CRT(210 * 2, 1, Outputs::CRT::DisplayType::PAL50, 1)),
crt_(new Outputs::CRT::CRT(206 * 2, 1, Outputs::CRT::DisplayType::PAL50, 1)),
line_data_(nullptr),
line_data_pointer_(nullptr),
cycles_since_update_(0),

17
Machines/ZX8081/ZX8081.cpp
View File

@ -32,6 +32,10 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
video_->run_for_cycles(cycle.length);
tape_player_.run_for_cycles(cycle.length);
static uint64_t time = 0;
time += (uint64_t)cycle.length;
static uint8_t last_input = 0xff;
uint16_t refresh = 0;
uint16_t address = cycle.address ? *cycle.address : 0;
switch(cycle.operation) {
@ -54,6 +58,13 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
}
value &= ~(tape_player_.get_input() ? 0x00 : 0x80);
// if((last_input ^ value) & 0x80) {
// printf("%lld\n", time);
// time = 0;
// last_input = value;
// }
// printf("[%02x]\n", value);
}
*cycle.value = value;
} break;
@ -65,9 +76,13 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
break;
case CPU::Z80::BusOperation::ReadOpcode:
// if(address >= 0x22f && address < 0x24d && count) {
// printf("%04x A:%02x BC:%04x DE:%04x\n", address, get_value_of_register(CPU::Z80::Register::A), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE));
// count--;
// }
set_hsync(false);
refresh = get_value_of_register(CPU::Z80::Register::Refresh);
set_interrupt_line(!(refresh & 0x40));
set_interrupt_line(!(refresh & 0x40), -2);
case CPU::Z80::BusOperation::Read:
if((address & 0xc000) == 0x0000) *cycle.value = rom_[address & (rom_.size() - 1)];
else if((address & 0x4000) == 0x4000) {