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Propagate to bitplanes immediately; fix odd/even confusion.
This commit is contained in:
Thomas Harte
parent
7c73ed7ed5
commit
dbae3fc9a5
@ -8,9 +8,9 @@
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#include "Chipset.hpp"
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//#ifndef NDEBUG
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//#define NDEBUG
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//#endif
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#ifndef NDEBUG
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#define NDEBUG
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#endif
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#define LOG_PREFIX "[Amiga chipset] "
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#include "../../Outputs/Log.hpp"
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@ -317,7 +317,18 @@ template <int cycle> void Chipset::output() {
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// video to 368 low resolution pixel"
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//
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// => 184 windows out of 227 are visible, which concurs.
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//
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// TODO: Reload bitplanes if anything is pending.
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// if(has_next_bitplanes_) {
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// has_next_bitplanes_ = false;
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// bitplane_pixels_.set(
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// previous_bitplanes_,
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// next_bitplanes_,
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// odd_delay_,
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// even_delay_
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// );
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// previous_bitplanes_ = next_bitplanes_;
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// }
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// Advance audio.
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audio_.output();
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@ -457,18 +468,6 @@ template <int cycle> void Chipset::output() {
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sprite_shifters_[1].shift();
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sprite_shifters_[2].shift();
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sprite_shifters_[3].shift();
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// Reload if anything is pending.
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if(has_next_bitplanes_) {
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has_next_bitplanes_ = false;
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bitplane_pixels_.set(
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previous_bitplanes_,
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next_bitplanes_,
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odd_delay_,
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even_delay_
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);
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previous_bitplanes_ = next_bitplanes_;
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}
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}
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void Chipset::flush_output() {
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@ -515,22 +514,66 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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if(cycle == fetch_window_[1]) fetch_stop_ = cycle + (is_high_res_ ? 12 : 8);
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fetch_horizontal_ &= cycle != fetch_stop_;
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if((dma_control_ & BitplaneFlag) == BitplaneFlag) {
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// TODO: offer a cycle for bitplane collection.
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// Probably need to indicate odd or even?
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if(fetch_vertical_ && fetch_horizontal_ && bitplanes_.advance_dma(cycle)) {
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did_fetch_ = true;
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return false;
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}
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}
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// Contradictory snippets from the Hardware Reference manual:
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//
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// 1)
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// The Copper is a two-cycle processor that requests the bus only during
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// odd-numbered memory cycles. This prevents collision with audio, disk,
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// refresh, sprites, and most low resolution display DMA access, all of which
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// use only the even-numbered memory cycles.
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//
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// 2)
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// |<- - - - - - - - average 68000 cycle - - - - - - - - ->|
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// | |
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// |<- - - - internal - - - ->|<- - - - - memory - - - ->|
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// | operation | access |
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// | portion | portion |
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// | | |
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// | odd cycle, | even cycle, |
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// | assigned to | available to |
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// | other devices | the 68000 |
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//
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// Figure 6-10: Normal 68000 Cycle
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// There's also Figure 6-9, which in theory nails down slot usage, but
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// numbers the boundaries between slots rather than the slots themselves...
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// and has nine slots depicted between positions $20 and $21. So
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// whether the boundary numbers assign to the slots on their left or on
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// their right is entirely opaque.
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// I therefore take the word of Toni Wilen via https://eab.abime.net/showpost.php?p=938307&postcount=2
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// as definitive: "CPU ... generally ... uses even [cycles] only".
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//
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// So probably the Copper requests the bus only on _even_ cycles?
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// General rule:
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//
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// Chipset work on odd cycles, 68000 access on even.
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//
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// Exceptions:
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//
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// Bitplanes, the Blitter if a flag is set.
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if constexpr (cycle & 1) {
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// Odd slot use/priority:
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//
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// 1. Bitplane fetches [dealt with above].
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// 2. Refresh, disk, audio, or sprites. Depending on region.
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// 2. Refresh, disk, audio, sprites or Copper. Depending on region.
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//
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// Blitter and CPU priority is dealt with below.
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if constexpr (cycle >= 0x07 && cycle < 0x0d) {
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if constexpr (cycle >= 0x00 && cycle < 0x08) {
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// Memory refresh, four slots per line.
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return true;
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}
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if constexpr (cycle >= 0x08 && cycle < 0x0e) {
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if((dma_control_ & DiskFlag) == DiskFlag) {
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if(disk_.advance_dma()) {
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return false;
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@ -538,9 +581,10 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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}
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}
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if constexpr (cycle >= 0xd && cycle < 0x14) {
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constexpr auto channel = (cycle - 0xd) >> 1;
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if constexpr (cycle >= 0xe && cycle < 0x16) {
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constexpr auto channel = (cycle - 0xe) >> 1;
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static_assert(channel >= 0 && channel < 4);
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static_assert(cycle != 0x15 || channel == 3);
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if((dma_control_ & AudioFlags[channel]) == AudioFlags[channel]) {
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if(audio_.advance_dma(channel)) {
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@ -549,23 +593,23 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
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}
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}
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if constexpr (cycle >= 0x15 && cycle < 0x35) {
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if constexpr (cycle >= 0x16 && cycle < 0x36) {
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if((dma_control_ & SpritesFlag) == SpritesFlag && y_ >= vertical_blank_height_) {
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constexpr auto sprite_id = (cycle - 0x15) >> 2;
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constexpr auto sprite_id = (cycle - 0x16) >> 2;
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static_assert(sprite_id >= 0 && sprite_id < std::tuple_size<decltype(sprites_)>::value);
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if(sprites_[sprite_id].advance_dma(cycle&2)) {
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if(sprites_[sprite_id].advance_dma(!(cycle&2))) {
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return false;
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}
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}
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}
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} else {
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// Bitplanes being dealt with, specific odd-cycle responsibility
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// Bitplanes having been dealt with, specific even-cycle responsibility
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// is just possibly to pass to the Copper.
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//
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// The Blitter and CPU are dealt with outside of the odd/even test.
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if((dma_control_ & CopperFlag) == CopperFlag) {
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if(copper_.advance_dma(uint16_t(((y_ & 0xff) << 8) | (cycle & 0xfe)), blitter_.get_status())) {
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if(copper_.advance_dma(uint16_t(((y_ & 0xff) << 8) | cycle), blitter_.get_status())) {
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return false;
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}
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} else {
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@ -726,11 +770,17 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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}
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void Chipset::post_bitplanes(const BitplaneData &data) {
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// Posted bitplanes should be received at the end of the
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// current memory slot. So put them aside for now, and
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// deal with them momentarily.
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has_next_bitplanes_ = true;
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// For now this retains the storage that'll be used when I switch to
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// deferred loading, but continues to act as if the Amiga were barrel
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// shifting bitplane data.
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next_bitplanes_ = data;
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bitplane_pixels_.set(
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previous_bitplanes_,
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next_bitplanes_,
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odd_delay_,
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even_delay_
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);
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previous_bitplanes_ = next_bitplanes_;
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}
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void Chipset::update_interrupts() {
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