From dc16928f7431440ff25524ae39ebc148c9463b3b Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Wed, 20 Apr 2022 16:56:26 -0400
Subject: [PATCH] Add appropriate exclusions for JSR, JMP, Scc.

---
 InstructionSets/68k/Decoder.cpp               | 25 +++++++++
 .../Mac/Clock SignalTests/m68kDecoderTests.mm | 52 +++++++++++++++++++
 2 files changed, 77 insertions(+)

diff --git a/InstructionSets/68k/Decoder.cpp b/InstructionSets/68k/Decoder.cpp
index ec06620ed..5f7562000 100644
--- a/InstructionSets/68k/Decoder.cpp
+++ b/InstructionSets/68k/Decoder.cpp
@@ -301,6 +301,31 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 				case AddressingMode::None:
 					return Preinstruction();
 			}
+
+		case OpT(Operation::JSR):	case OpT(Operation::JMP):
+			switch(original.mode<0>()) {
+				default: return original;
+
+				case AddressingMode::DataRegisterDirect:
+				case AddressingMode::AddressRegisterDirect:
+				case AddressingMode::AddressRegisterIndirectWithPostincrement:
+				case AddressingMode::AddressRegisterIndirectWithPredecrement:
+				case AddressingMode::ImmediateData:
+				case AddressingMode::None:
+					return Preinstruction();
+			}
+
+		case OpT(Operation::Scc):
+			switch(original.mode<0>()) {
+				default: return original;
+
+				case AddressingMode::AddressRegisterDirect:
+				case AddressingMode::ImmediateData:
+				case AddressingMode::ProgramCounterIndirectWithDisplacement:
+				case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
+				case AddressingMode::None:
+					return Preinstruction();
+			}
 	}
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
index 94d1c7feb..793de0f58 100644
--- a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm	
@@ -149,6 +149,58 @@ template <int index> NSString *operand(Preinstruction instruction) {
 			case Operation::TSTw:	instruction = @"TST.w";	break;
 			case Operation::TSTl:	instruction = @"TST.l";	break;
 
+			case Operation::JMP:	instruction = @"JMP";	break;
+			case Operation::JSR:	instruction = @"JSR";	break;
+			case Operation::RTS:	instruction = @"RTS";	break;
+			case Operation::DBcc:	instruction = @"DBcc";	break;
+			case Operation::Scc:	instruction = @"Scc";	break;
+
+			/*
+				TODO:
+
+				Bccb,	Bccl,	Bccw,
+				BSRb,	BSRl,	BSRw,
+
+				CLRb, CLRw, CLRl,
+				NEGXb, NEGXw, NEGXl,
+				NEGb, NEGw, NEGl,
+
+				ASLb, ASLw, ASLl, ASLm,
+				ASRb, ASRw, ASRl, ASRm,
+				LSLb, LSLw, LSLl, LSLm,
+				LSRb, LSRw, LSRl, LSRm,
+				ROLb, ROLw, ROLl, ROLm,
+				RORb, RORw, RORl, RORm,
+				ROXLb, ROXLw, ROXLl, ROXLm,
+				ROXRb, ROXRw, ROXRl, ROXRm,
+
+				MOVEMl, MOVEMw,
+				MOVEPl, MOVEPw,
+
+				ANDb,	ANDw,	ANDl,
+				EORb,	EORw,	EORl,
+				NOTb, 	NOTw, 	NOTl,
+				ORb,	ORw,	ORl,
+
+				MULU,	MULS,
+				DIVU,	DIVS,
+
+				RTE,	RTR,
+
+				TRAP,	TRAPV,
+				CHK,
+
+				EXG,	SWAP,
+
+				TAS,
+
+				EXTbtow,	EXTwtol,
+
+				LINKw,	UNLINK,
+
+				STOP,	RESET,
+			*/
+
 			// For now, skip any unmapped operations.
 			default: continue;
 		}