mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Does the easier part of the easier half of 8086 decoding.
This commit is contained in:
Thomas Harte
parent
a41be61f99
commit
dc9d370952
@ -183,6 +183,8 @@
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@ -2324,6 +2328,15 @@
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path = Bridges;
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sourceTree = "<group>";
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};
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4B3F76AD25A0196100178AEC /* x86.cpp */,
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path = x86;
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@ -3892,6 +3905,7 @@
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4BDDBBD4259D757800CEFF58 /* PowerPC */,
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4B3F76AB25A0196100178AEC /* x86 */,
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path = Decoders;
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sourceTree = "<group>";
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@ -4666,6 +4680,7 @@
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4B0F94FF208C1A1600FE41D9 /* NIB.cpp in Sources */,
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4B0E04EB1FC9E78800F43484 /* CAS.cpp in Sources */,
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4BB0A65D2045009000FB3688 /* ColecoVision.cpp in Sources */,
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4B3F76AF25A0196100178AEC /* x86.cpp in Sources */,
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4BB0A65C2044FD3000FB3688 /* SN76489.cpp in Sources */,
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4B595FAE2086DFBA0083CAA8 /* AudioToggle.cpp in Sources */,
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4B055AB91FAE86170060FFFF /* Acorn.cpp in Sources */,
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@ -4738,6 +4753,7 @@
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4B54C0BF1F8D8F450050900F /* Keyboard.cpp in Sources */,
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4B3FE75E1F3CF68B00448EE4 /* CPM.cpp in Sources */,
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4B3F76AE25A0196100178AEC /* x86.cpp in Sources */,
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4BAE49582032881E004BE78E /* CSZX8081.mm in Sources */,
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126
Processors/Decoders/x86/x86.cpp
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126
Processors/Decoders/x86/x86.cpp
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@ -0,0 +1,126 @@
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//
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// x86.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/1/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "x86.hpp"
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using namespace CPU::Decoder::x86;
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Instruction Decoder::decode(uint8_t *source, size_t length) {
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uint8_t *const limit = source + length;
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#define MapPartial(value, op, sz, fmt, phs) \
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case value: \
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operation_ = Operation::op; \
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operand_size_ = Size::sz; \
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format_ = Format::fmt; \
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phase_ = Phase::phs; \
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break;
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#define MapComplete(value, op, sz, src, dest) \
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case value: \
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operation_ = Operation::op; \
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operand_size_ = Size::sz; \
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source_ = Source::src; \
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destination_ = Source::dest; \
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phase_ = Phase::ReadyToPost; \
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break;
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while(phase_ == Phase::Instruction && source != limit) {
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switch(*source) {
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#define PartialBlock(start, operation) \
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MapPartial(start + 0x00, operation, Byte, MemReg_Reg, ModRM); \
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MapPartial(start + 0x01, operation, Word, MemReg_Reg, ModRM); \
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MapPartial(start + 0x02, operation, Byte, Reg_MemReg, ModRM); \
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MapPartial(start + 0x03, operation, Word, Reg_MemReg, ModRM); \
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MapPartial(start + 0x04, operation, Byte, Ac_Data, AwaitingOperands); \
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MapPartial(start + 0x05, operation, Word, Ac_Data, AwaitingOperands);
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PartialBlock(0x00, ADD);
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MapComplete(0x06, PUSH, Word, ES, None);
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MapComplete(0x07, POP, Word, ES, None);
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PartialBlock(0x08, OR);
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MapComplete(0x0e, PUSH, Word, CS, None);
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/* 0x0f: not used. */
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PartialBlock(0x10, ADC);
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MapComplete(0x16, PUSH, Word, SS, None);
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MapComplete(0x17, POP, Word, SS, None);
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PartialBlock(0x18, SBB);
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MapComplete(0x1e, PUSH, Word, DS, None);
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MapComplete(0x1f, POP, Word, DS, None);
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PartialBlock(0x20, AND);
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case 0x26: segment_override_ = Source::ES; break;
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MapComplete(0x27, DAA, Implied, None, None);
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PartialBlock(0x28, SUB);
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case 0x2e: segment_override_ = Source::CS; break;
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MapComplete(0x2f, DAS, Implied, None, None);
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PartialBlock(0x30, XOR);
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case 0x36: segment_override_ = Source::SS; break;
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MapComplete(0x37, AAA, Implied, None, None);
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PartialBlock(0x38, CMP);
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case 0x3e: segment_override_ = Source::DS; break;
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MapComplete(0x3f, AAS, Implied, None, None);
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#undef PartialBlock
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#define RegisterBlock(start, operation) \
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MapComplete(start + 0x00, operation, Word, AX, AX); \
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MapComplete(start + 0x01, operation, Word, CX, CX); \
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MapComplete(start + 0x02, operation, Word, DX, DX); \
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MapComplete(start + 0x03, operation, Word, BX, BX); \
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MapComplete(start + 0x04, operation, Word, SP, SP); \
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MapComplete(start + 0x05, operation, Word, BP, BP); \
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MapComplete(start + 0x06, operation, Word, SI, SI); \
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MapComplete(start + 0x07, operation, Word, DI, DI); \
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RegisterBlock(0x40, INC);
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RegisterBlock(0x48, DEC);
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RegisterBlock(0x50, PUSH);
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RegisterBlock(0x58, POP);
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#undef RegisterBlock
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/* 0x60–0x6f: not used. */
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MapPartial(0x70, JO, Byte, Disp, AwaitingOperands);
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MapPartial(0x71, JNO, Byte, Disp, AwaitingOperands);
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MapPartial(0x72, JB, Byte, Disp, AwaitingOperands);
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MapPartial(0x73, JNB, Byte, Disp, AwaitingOperands);
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MapPartial(0x74, JE, Byte, Disp, AwaitingOperands);
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MapPartial(0x75, JNE, Byte, Disp, AwaitingOperands);
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MapPartial(0x76, JBE, Byte, Disp, AwaitingOperands);
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MapPartial(0x77, JNBE, Byte, Disp, AwaitingOperands);
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MapPartial(0x78, JS, Byte, Disp, AwaitingOperands);
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MapPartial(0x79, JNS, Byte, Disp, AwaitingOperands);
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MapPartial(0x7a, JP, Byte, Disp, AwaitingOperands);
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MapPartial(0x7b, JNP, Byte, Disp, AwaitingOperands);
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MapPartial(0x7c, JL, Byte, Disp, AwaitingOperands);
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MapPartial(0x7d, JNL, Byte, Disp, AwaitingOperands);
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MapPartial(0x7e, JLE, Byte, Disp, AwaitingOperands);
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MapPartial(0x7f, JNLE, Byte, Disp, AwaitingOperands);
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}
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++source;
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++consumed_;
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}
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#undef MapInstr
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if(phase_ == Phase::ReadyToPost) {
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// TODO: construct actual Instruction.
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}
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return Instruction();
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}
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127
Processors/Decoders/x86/x86.hpp
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127
Processors/Decoders/x86/x86.hpp
Normal file
@ -0,0 +1,127 @@
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//
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// x86.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 1/1/21.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef x86_hpp
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#define x86_hpp
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#include <cstddef>
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#include <cstdint>
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namespace CPU {
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namespace Decoder {
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namespace x86 {
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enum class Model {
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i8086,
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};
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enum class Operation: uint8_t {
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Invalid,
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AAA, AAD, AAM, AAS, ADC, ADD, AND, CALL, CBW, CLC, CLD, CLI, CMC,
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CMP, CMPS, CWD, DAA, DAS, DEC, DIV, ESC, HLT, IDIV, IMUL, IN,
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INC, INT, INTO, IRET,
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JO, JNO,
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JB, JNB,
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JE, JNE,
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JBE, JNBE,
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JS, JNS,
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JP, JNP,
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JL, JNL,
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JLE, JNLE,
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JMP, JCXZ,
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LAHF, LDS, LEA,
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LODS, LOOPE, LOOPNE, MOV, MOVS, MUL, NEG, NOP, NOT, OR, OUT,
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POP, POPF, PUSH, PUSHF, RCL, RCR, REP, RET, ROL, ROR, SAHF,
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SAR, SBB, SCAS, SHL, SHR, STC, STD, STI, STOS, SUB, TEST,
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WAIT, XCHG, XLAT, XOR
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};
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enum class Size: uint8_t {
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Implied = 0,
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Byte = 1,
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Word = 2,
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};
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enum class Source: uint8_t {
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None,
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AL, AH, AX,
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BL, BH, BX,
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CL, CH, CX,
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DL, DH, DX,
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CS, DS, ES, SS,
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SI, DI,
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BP, SP,
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Memory, Immediate
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};
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class Instruction {
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public:
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const Operation operation = Operation::Invalid;
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const Size operand_size = Size::Byte;
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const Source source = Source::AL;
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const Source destination = Source::AL;
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int size() const {
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return size_;
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}
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private:
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int size_ = 0;
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};
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/*!
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Implements Intel x86 instruction decoding.
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This is an experimental implementation; it has not yet undergone significant testing.
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*/
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struct Decoder {
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public:
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Decoder(Model model);
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/*!
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@returns an @c Instruction with a positive size to indicate successful decoding; a
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negative size specifies the number of further bytes required fully to decode, and
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a zero size indicates that further bytes are required but the decoder does not yet
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know exactly how many.
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*/
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Instruction decode(uint8_t *source, size_t length);
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private:
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enum class Phase {
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Instruction,
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ModRM,
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AwaitingOperands,
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ReadyToPost
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} phase_ = Phase::Instruction;
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enum class Format: uint8_t {
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MemReg_Reg,
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Reg_MemReg,
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Ac_Data,
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MemReg_Data,
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Disp
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} format_ = Format::MemReg_Reg;
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int consumed_ = 0;
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Operation operation_ = Operation::Invalid;
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Size operand_size_ = Size::Implied;
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Source source_ = Source::None;
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Source destination_ = Source::None;
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Source segment_override_ = Source::None;
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};
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}
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}
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}
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#endif /* x86_hpp */
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