1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 16:31:42 +00:00

Adds input line capture.

This commit is contained in:
Thomas Harte 2020-05-16 17:44:15 -04:00
parent f7a16762b4
commit dcc0ee3679
2 changed files with 30 additions and 5 deletions

View File

@ -11,6 +11,7 @@
using namespace CPU::MC68000;
State::State(const ProcessorBase &src): State() {
// Registers.
for(int c = 0; c < 7; ++c) {
registers.address[c] = src.address_[c].full;
registers.data[c] = src.data_[c].full;
@ -21,6 +22,15 @@ State::State(const ProcessorBase &src): State() {
registers.status = src.get_status();
registers.program_counter = src.program_counter_.full;
registers.prefetch = src.prefetch_queue_.full;
// Inputs.
inputs.bus_interrupt_level = uint8_t(src.bus_interrupt_level_);
inputs.dtack = src.dtack_;
inputs.is_peripheral_address = src.is_peripheral_address_;
inputs.bus_error = src.bus_error_;
inputs.bus_request = src.bus_request_;
inputs.bus_grant = false; // TODO (within the 68000).
inputs.halt = src.halt_;
}
void State::apply(ProcessorBase &target) {
@ -47,12 +57,19 @@ State::Registers::Registers() {
}
}
State::Inputs::Inputs() {
if(needs_declare()) {
DeclareField(bus_interrupt_level);
DeclareField(dtack);
DeclareField(is_peripheral_address);
DeclareField(bus_error);
DeclareField(bus_request);
DeclareField(bus_grant);
DeclareField(halt);
}
}
State::ExecutionState::ExecutionState() {
if(needs_declare()) {
}
}
State::Inputs::Inputs() {
if(needs_declare()) {
}
}

View File

@ -43,6 +43,14 @@ struct State: public Reflection::StructImpl<State> {
related to an access cycle.
*/
struct Inputs: public Reflection::StructImpl<Inputs> {
uint8_t bus_interrupt_level;
bool dtack;
bool is_peripheral_address;
bool bus_error;
bool bus_request;
bool bus_grant;
bool halt;
Inputs();
} inputs;