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Merge pull request #364 from TomHarte/TimingUpfront

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Ensures the Coleco & MSX account for instruction lengths prior to outward accesses.
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Thomas Harte 2018-03-07 17:29:32 -05:00 committed by GitHub
commit dd6f85d4db
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2 changed files with 14 additions and 14 deletions
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6
Machines/ColecoVision/ColecoVision.cpp
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@ -192,6 +192,9 @@ class ConcreteMachine:
// MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
time_since_vdp_update_ += cycle.length;
time_since_sn76489_update_ += cycle.length;
uint16_t address = cycle.address ? *cycle.address : 0x0000;
switch(cycle.operation) {
case CPU::Z80::PartialMachineCycle::ReadOpcode:
@ -313,9 +316,6 @@ class ConcreteMachine:
default: break;
}
time_since_vdp_update_ += cycle.length;
time_since_sn76489_update_ += cycle.length;
if(time_until_interrupt_ > 0) {
time_until_interrupt_ -= cycle.length;
if(time_until_interrupt_ <= HalfCycles(0)) {

22
Machines/MSX/MSX.cpp
View File

@ -282,6 +282,17 @@ class ConcreteMachine:
// MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
// but otherwise runs without pause.
const HalfCycles addition((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);
const HalfCycles total_length = addition + cycle.length;
time_since_vdp_update_ += total_length;
time_since_ay_update_ += total_length;
memory_slots_[0].cycles_since_update += total_length;
memory_slots_[1].cycles_since_update += total_length;
memory_slots_[2].cycles_since_update += total_length;
memory_slots_[3].cycles_since_update += total_length;
uint16_t address = cycle.address ? *cycle.address : 0x0000;
switch(cycle.operation) {
case CPU::Z80::PartialMachineCycle::ReadOpcode:
@ -459,23 +470,12 @@ class ConcreteMachine:
if(!tape_player_is_sleeping_)
tape_player_.run_for(cycle.length.as_int());
// Per the best information I currently have, the MSX inserts an extra cycle into each opcode read,
// but otherwise runs without pause.
const HalfCycles addition((cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) ? 2 : 0);
const HalfCycles total_length = addition + cycle.length;
if(time_until_interrupt_ > 0) {
time_until_interrupt_ -= total_length;
if(time_until_interrupt_ <= HalfCycles(0)) {
z80_.set_interrupt_line(true, time_until_interrupt_);
}
}
time_since_vdp_update_ += total_length;
time_since_ay_update_ += total_length;
memory_slots_[0].cycles_since_update += total_length;
memory_slots_[1].cycles_since_update += total_length;
memory_slots_[2].cycles_since_update += total_length;
memory_slots_[3].cycles_since_update += total_length;
return addition;
}