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Reshuffles enum to make macro tests marginally easier.

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This commit is contained in:
Thomas Harte 2020-11-03 20:17:09 -05:00
parent 5cbb91f352
commit ddc44ce0d1
2 changed files with 32 additions and 30 deletions
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44
Processors/6502/AllRAM/6502AllRAM.cpp
View File

@ -11,7 +11,7 @@
#include <algorithm>
#include <cstring>
//#define BE_NOISY
#define BE_NOISY
using namespace CPU::MOS6502;
@ -30,33 +30,35 @@ template <Type type> class ConcreteAllRAMProcessor: public AllRAMProcessor, publ
inline Cycles perform_bus_operation(BusOperation operation, uint32_t address, uint8_t *value) {
timestamp_ += Cycles(1);
if(operation == BusOperation::ReadOpcode) {
if(isAccessOperation(operation)) {
if(operation == BusOperation::ReadOpcode) {
#ifdef BE_NOISY
printf("[%04x] %02x a:%04x x:%04x y:%04x p:%02x s:%02x\n", address, memory_[address],
mos6502_.get_value_of_register(Register::A),
mos6502_.get_value_of_register(Register::X),
mos6502_.get_value_of_register(Register::Y),
mos6502_.get_value_of_register(Register::Flags) & 0xff,
mos6502_.get_value_of_register(Register::StackPointer) & 0xff);
printf("[%04x] %02x a:%04x x:%04x y:%04x p:%02x s:%02x\n", address, memory_[address],
mos6502_.get_value_of_register(Register::A),
mos6502_.get_value_of_register(Register::X),
mos6502_.get_value_of_register(Register::Y),
mos6502_.get_value_of_register(Register::Flags) & 0xff,
mos6502_.get_value_of_register(Register::StackPointer) & 0xff);
#endif
check_address_for_trap(address);
--instructions_;
}
check_address_for_trap(address);
--instructions_;
}
if(isReadOperation(operation)) {
*value = memory_[address];
if(isReadOperation(operation)) {
*value = memory_[address];
#ifdef BE_NOISY
// if((address&0xff00) == 0x100) {
printf("%04x -> %02x\n", address, *value);
// }
// if((address&0xff00) == 0x100) {
printf("%04x -> %02x\n", address, *value);
// }
#endif
} else {
memory_[address] = *value;
} else {
memory_[address] = *value;
#ifdef BE_NOISY
// if((address&0xff00) == 0x100) {
printf("%04x <- %02x\n", address, *value);
// }
// if((address&0xff00) == 0x100) {
printf("%04x <- %02x\n", address, *value);
// }
#endif
}
}
return Cycles(1);

18
Processors/6502Esque/6502Esque.hpp
View File

@ -83,19 +83,19 @@ enum BusOperation {
/// 65816: indicates that a read was signalled, but neither VDA nor VPA were active.
InternalOperationRead,
/// 6502: indicates that a write was signalled.
/// 65816: indicates that a write was signalled with VDA.
Write,
/// 6502: never signalled.
/// 65816: indicates that a write was signalled, but neither VDA nor VPA were active.
InternalOperationWrite,
/// All processors: indicates that the processor is paused due to the RDY input.
/// 65C02 and 65816: indicates a WAI is ongoing.
Ready,
/// 65C02 and 65816: indicates a STP condition.
None,
/// 6502: indicates that a write was signalled.
/// 65816: indicates that a write was signalled with VDA.
Write,
/// 6502: never signalled.
/// 65816: indicates that a write was signalled, but neither VDA nor VPA were active.
InternalOperationWrite,
};
/*!
@ -106,12 +106,12 @@ enum BusOperation {
/*!
For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
*/
#define isWriteOperation(v) (v == CPU::MOS6502Esque::Write || v == CPU::MOS6502Esque::InternalOperationWrite)
#define isWriteOperation(v) (v >= CPU::MOS6502Esque::Write)
/*!
Evaluates to @c true if the operation actually expects a response; @c false otherwise.
*/
#define isAccessOperation(v) ((v < CPU::MOS6502Esque::Ready) && (v != CPU::MOS6502Esque::InternalOperationRead) && (v != CPU::MOS6502Esque::InternalOperationWrite))
#define isAccessOperation(v) ((v <= CPU::MOS6502Esque::ReadVector) || (v == CPU::MOS6502Esque::Write))
/*!
A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,