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Attempts implementations of both ready and abort.
Which I think concludes the inputs?
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@ -35,6 +35,7 @@ class ProcessorBase: protected ProcessorStorage {
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inline void set_nmi_line(bool);
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inline void set_reset_line(bool);
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inline void set_abort_line(bool);
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inline bool get_is_resetting() const;
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void set_value_of_register(Register r, uint16_t value);
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inline bool is_jammed() const;
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@ -25,6 +25,13 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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Cycles number_of_cycles = cycles + cycles_left_to_run_;
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while(number_of_cycles > Cycles(0)) {
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// Wait for ready to be inactive before proceeding.
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while(uses_ready_line && ready_line_ && number_of_cycles > Cycles(0)) {
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number_of_cycles -= bus_handler_.perform_bus_operation(BusOperation::Ready, bus_address_, &bus_throwaway_);
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}
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// Process for as much time is left and/or until ready is signalled.
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while((!uses_ready_line || !ready_line_) && number_of_cycles > Cycles(0)) {
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const MicroOp operation = *next_op_;
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++next_op_;
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@ -374,6 +381,8 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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// to a 6502 but may not have the exact details correct. E.g. if IRQ has
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// become inactive since the decision was made to start an interrupt, should
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// that turn into a BRK?
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//
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// Also: priority here is a guess.
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bool is_brk = false;
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@ -383,17 +392,23 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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set_reset_state();
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} else if(pending_exceptions_ & NMI) {
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pending_exceptions_ &= ~NMI;
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data_address_ = 0xfffa;
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data_address_ = registers_.emulation_flag ? 0xfffa : 0xffea;
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} else if(pending_exceptions_ & IRQ & registers_.flags.inverse_interrupt) {
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pending_exceptions_ &= ~IRQ;
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data_address_ = 0xfffe;
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data_address_ = registers_.emulation_flag ? 0xfffe : 0xffee;
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} else if(pending_exceptions_ & Abort) {
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// Special case: restore registers from start of instruction.
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registers_ = abort_registers_copy_;
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pending_exceptions_ &= ~Abort;
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data_address_ = registers_.emulation_flag ? 0xfff8 : 0xffe8;;
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} else {
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is_brk = active_instruction_ == instructions; // Given that BRK has opcode 00.
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if(is_brk) {
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data_address_ = registers_.emulation_flag ? 0xfffe : 0xfff6;
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data_address_ = registers_.emulation_flag ? 0xfffe : 0xffe6;
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} else {
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// Implicitly: COP.
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data_address_ = 0xfff4;
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data_address_ = registers_.emulation_flag ? 0xfff4 : 0xffe8;
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}
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}
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@ -900,8 +915,7 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
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// next thing is a MoveToNextProgram.
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selected_exceptions_ = pending_exceptions_ & (registers_.flags.inverse_interrupt | PowerOn | Reset | NMI);
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number_of_cycles -= bus_handler_.perform_bus_operation(bus_operation_, bus_address_, bus_value_);
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// TODO: RDY line.
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}
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}
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#undef read
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@ -947,5 +961,26 @@ void ProcessorBase::set_nmi_line(bool active) {
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}
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}
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void ProcessorBase::set_abort_line(bool active) {
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// Take a copy of register state now to restore at the beginning of the exception
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// if abort has gone active, preparing to regress the program counter.
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if(active) {
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pending_exceptions_ |= Abort;
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abort_registers_copy_ = registers_;
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abort_registers_copy_.pc = last_operation_pc_;
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} else {
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pending_exceptions_ &= ~Abort;
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}
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}
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template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler, uses_ready_line>::set_ready_line(bool active) {
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assert(uses_ready_line);
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ready_line_ = active;
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}
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// The 65816 can't jam.
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bool ProcessorBase::is_jammed() const { return false; }
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bool ProcessorBase::get_is_resetting() const {
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return pending_exceptions_ & (Reset | PowerOn);
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}
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