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Ensure appropriate data bus size.

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This commit is contained in:
Thomas Harte 2022-06-25 21:07:29 -04:00
parent 9cf64ea643
commit e0ec3c986d
1 changed files with 3 additions and 1 deletions
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4
Processors/6502/AllRAM/6502AllRAM.cpp
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@ -29,6 +29,8 @@ template <Type type, bool has_cias> class ConcreteAllRAMProcessor:
public AllRAMProcessor, public CPU::MOS6502Esque::BusHandlerT<type> public AllRAMProcessor, public CPU::MOS6502Esque::BusHandlerT<type>
{ {
public: public:
using typename CPU::MOS6502Esque::BusHandlerT<type>::AddressType;
ConcreteAllRAMProcessor(size_t memory_size) : ConcreteAllRAMProcessor(size_t memory_size) :
AllRAMProcessor(memory_size), AllRAMProcessor(memory_size),
mos6502_(*this), mos6502_(*this),
@ -37,7 +39,7 @@ template <Type type, bool has_cias> class ConcreteAllRAMProcessor:
mos6502_.set_power_on(false); mos6502_.set_power_on(false);
} }
inline Cycles perform_bus_operation(BusOperation operation, uint32_t address, uint8_t *value) { Cycles perform_bus_operation(BusOperation operation, AddressType address, uint8_t *value) {
timestamp_ += Cycles(1); timestamp_ += Cycles(1);
if constexpr (has_cias) { if constexpr (has_cias) {