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Implements phase-match bit.

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Seemingly causing the command phase to proceed.
This commit is contained in:
Thomas Harte 2019-08-18 23:15:54 -04:00
parent 90cf99b626
commit e3d9254555
2 changed files with 18 additions and 12 deletions
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2
Components/5380/DirectAccessDevice.cpp
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@ -59,7 +59,7 @@ void DirectAccessDevice::scsi_bus_did_change(Bus *, BusState new_state) {
// If request and acknowledge are both enabled, grab a byte and cancel the request. // If request and acknowledge are both enabled, grab a byte and cancel the request.
case Line::Request | Line::Acknowledge: case Line::Request | Line::Acknowledge:
bus_state_ &= ~Line::Request; bus_state_ &= ~Line::Request;
printf("Got %02x maybe?\n", bus_state_ & 0xff); printf("Got %02x maybe?\n", new_state & 0xff);
// TODO: is the command phase over? // TODO: is the command phase over?
break; break;

28
Components/5380/ncr5380.cpp
View File

@ -19,7 +19,7 @@ NCR5380::NCR5380(int clock_rate) :
} }
void NCR5380::write(int address, uint8_t value) { void NCR5380::write(int address, uint8_t value) {
using Line = SCSI::Line; using SCSI::Line;
switch(address & 7) { switch(address & 7) {
case 0: case 0:
LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value)); LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
@ -112,6 +112,7 @@ void NCR5380::write(int address, uint8_t value) {
} }
uint8_t NCR5380::read(int address) { uint8_t NCR5380::read(int address) {
using SCSI::Line;
switch(address & 7) { switch(address & 7) {
case 0: case 0:
LOG("[SCSI 0] Get current SCSI bus state"); LOG("[SCSI 0] Get current SCSI bus state");
@ -146,23 +147,28 @@ uint8_t NCR5380::read(int address) {
case 4: { case 4: {
const auto bus_state = bus_.get_state(); const auto bus_state = bus_.get_state();
const uint8_t result = const uint8_t result =
((bus_state & SCSI::Line::Reset) ? 0x80 : 0x00) | ((bus_state & Line::Reset) ? 0x80 : 0x00) |
((bus_state & SCSI::Line::Busy) ? 0x40 : 0x00) | ((bus_state & Line::Busy) ? 0x40 : 0x00) |
((bus_state & SCSI::Line::Request) ? 0x20 : 0x00) | ((bus_state & Line::Request) ? 0x20 : 0x00) |
((bus_state & SCSI::Line::Message) ? 0x10 : 0x00) | ((bus_state & Line::Message) ? 0x10 : 0x00) |
((bus_state & SCSI::Line::Control) ? 0x08 : 0x00) | ((bus_state & Line::Control) ? 0x08 : 0x00) |
((bus_state & SCSI::Line::Input) ? 0x04 : 0x00) | ((bus_state & Line::Input) ? 0x04 : 0x00) |
((bus_state & SCSI::Line::SelectTarget) ? 0x02 : 0x00) | ((bus_state & Line::SelectTarget) ? 0x02 : 0x00) |
((bus_state & SCSI::Line::Parity) ? 0x01 : 0x00); ((bus_state & Line::Parity) ? 0x01 : 0x00);
LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result)); LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result));
return result; return result;
} }
case 5: { case 5: {
const auto bus_state = bus_.get_state(); const auto bus_state = bus_.get_state();
const bool phase_matches =
(bus_output_ & (Line::Message | Line::Control | Line::Input)) ==
(bus_state & (Line::Message | Line::Control | Line::Input));
const uint8_t result = const uint8_t result =
((bus_state & SCSI::Line::Attention) ? 0x02 : 0x00) | (phase_matches ? 0x08 : 0x00) |
((bus_state & SCSI::Line::Acknowledge) ? 0x01 : 0x00); ((bus_state & Line::Attention) ? 0x02 : 0x00) |
((bus_state & Line::Acknowledge) ? 0x01 : 0x00);
LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result)); LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result));
return result; return result;
} }