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Assume and test that divide-by-zero posts the PC of the offending instruction.
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@ -880,14 +880,27 @@
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- (void)testDIVSException {
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// DIVS.W #0, D1
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self.machine->set_initial_stack_pointer(0);
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const uint32_t initial_sp = 0x5000;
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self.machine->set_initial_stack_pointer(initial_sp);
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[self performDIVS:0x0 d1:0x1fffffff];
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// Check register state.
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const auto state = self.machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x1fffffff);
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XCTAssertEqual(state.supervisor_stack_pointer, 0xfffffffa);
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XCTAssertEqual(state.supervisor_stack_pointer, initial_sp - 6);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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XCTAssertEqual(42, self.machine->get_cycle_count());
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// Check stack contents; should be PC.l, PC.h and status register.
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// Assumed: the program counter on the stack is that of the
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// failing instrustion.
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const uint16_t pc_h = *self.machine->ram_at(initial_sp-4);
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const uint16_t pc_l = *self.machine->ram_at(initial_sp-2);
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// const uint16_t status = *self.machine->ram_at(initial_sp);
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const uint32_t initial_pc = self.machine->initial_pc();
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XCTAssertEqual(pc_l, initial_pc & 0xffff);
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XCTAssertEqual(pc_h, initial_pc >> 16);
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// XCTAssertEqual(status, 9);
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}
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@end
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@ -35,6 +35,10 @@ class RAM68000: public CPU::MC68000::BusHandler {
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set_processor_state(state);
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}
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uint32_t initial_pc() const {
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return 0x1000;
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}
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void set_program(const std::vector<uint16_t> &program) {
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memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t));
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@ -1000,7 +1000,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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populate_trap_steps(5, status()); \
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bus_program->microcycle.length = HalfCycles(20); \
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\
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program_counter_.full -= 2;
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program_counter_.full -= 6;
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case Operation::DIVU: {
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carry_flag_ = 0;
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