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Slightly clarifies logic.
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parent
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commit
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@ -348,13 +348,12 @@ class ConcreteMachine:
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cycle.set_value8_high(ay_.get_data_output());
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cycle.set_value8_high(ay_.get_data_output());
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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} else {
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} else {
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if(!(address&2)) {
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// Net effect here: addresses with bit 1 set write to a register,
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// Select register.
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// addresses with bit 1 clear select a register.
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ay_.set_control_lines(GI::AY38910::BC1);
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ay_.set_control_lines(GI::AY38910::ControlLines(
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} else {
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GI::AY38910::BC2 | GI::AY38910::BDIR
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// Write data to register.
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| ((address&2) ? 0 : GI::AY38910::BC1)
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ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BDIR));
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));
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}
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ay_.set_data_input(cycle.value8_high());
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ay_.set_data_input(cycle.value8_high());
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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ay_.set_control_lines(GI::AY38910::ControlLines(0));
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}
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}
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