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Slightly clarifies logic.

This commit is contained in:
Thomas Harte 2020-01-04 21:32:34 -05:00
parent 7b2777ac08
commit e4349f5e05

View File

@ -348,13 +348,12 @@ class ConcreteMachine:
cycle.set_value8_high(ay_.get_data_output()); cycle.set_value8_high(ay_.get_data_output());
ay_.set_control_lines(GI::AY38910::ControlLines(0)); ay_.set_control_lines(GI::AY38910::ControlLines(0));
} else { } else {
if(!(address&2)) { // Net effect here: addresses with bit 1 set write to a register,
// Select register. // addresses with bit 1 clear select a register.
ay_.set_control_lines(GI::AY38910::BC1); ay_.set_control_lines(GI::AY38910::ControlLines(
} else { GI::AY38910::BC2 | GI::AY38910::BDIR
// Write data to register. | ((address&2) ? 0 : GI::AY38910::BC1)
ay_.set_control_lines(GI::AY38910::ControlLines(GI::AY38910::BC2 | GI::AY38910::BDIR)); ));
}
ay_.set_data_input(cycle.value8_high()); ay_.set_data_input(cycle.value8_high());
ay_.set_control_lines(GI::AY38910::ControlLines(0)); ay_.set_control_lines(GI::AY38910::ControlLines(0));
} }