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Implement JSR.
This commit is contained in:
Thomas Harte
parent
0e4cfde657
commit
e46a3c4046
@ -156,7 +156,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
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// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
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_fileSet = [NSSet setWithArray:@[
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@"movem.json",
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@"chk.json",
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// Below this line are passing tests.
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@"abcd_sbcd.json",
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@ -171,12 +171,14 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
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@"eor_and_or.json",
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@"eori_andi_ori.json",
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@"ext.json",
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@"jsr.json",
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@"movem.json",
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@"movep.json",
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@"nbcd.json",
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@"ext.json",
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@"swap.json",
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]]; // 16/32 = 50 % done, as far as the tests go.
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// _testSet = [NSSet setWithArray:@[@"MOVEM 00fa (13)"]];
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]]; // 18/32 = 56 % done, as far as the tests go.
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// _testSet = [NSSet setWithArray:@[@"MOVEM 0067 (5)"]];
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}
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- (void)testAll {
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@ -287,7 +289,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
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NSNumber *const value = [enumerator nextObject];
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if(!address || !value) break;
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// XCTAssertEqual(test68000->ram[address.integerValue ^ 1], value.integerValue, @"%@: Memory at location %@ inconsistent", name, address);
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XCTAssertEqual(test68000->ram[address.integerValue ^ 1], value.integerValue, @"%@: Memory at location %@ inconsistent", name, address);
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if(test68000->ram[address.integerValue ^ 1] != value.integerValue) [_failures addObject:name];
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}
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@ -134,6 +134,15 @@ enum ExecutionState: int {
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BSR,
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JSRAddressRegisterIndirect,
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JSRAddressRegisterIndirectWithDisplacement,
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JSRAddressRegisterIndirectWithIndex8bitDisplacement,
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JSRProgramCounterIndirectWithDisplacement,
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JSRProgramCounterIndirectWithIndex8bitDisplacement,
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JSRAbsoluteShort,
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JSRAbsoluteLong,
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JSR_push,
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BCHG_BSET_Dn,
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BCLR_Dn,
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@ -587,6 +596,27 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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StdCASE(BSRb, perform_state_ = BSR);
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StdCASE(BSRw, perform_state_ = BSR);
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StdCASE(JSR, {
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switch(instruction_.mode(0)) {
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case Mode::AddressRegisterIndirect:
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MoveToState(JSRAddressRegisterIndirect);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(JSRAddressRegisterIndirectWithDisplacement);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(JSRAddressRegisterIndirectWithIndex8bitDisplacement);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(JSRProgramCounterIndirectWithDisplacement);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(JSRProgramCounterIndirectWithIndex8bitDisplacement);
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case Mode::AbsoluteShort:
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MoveToState(JSRAbsoluteShort);
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case Mode::AbsoluteLong:
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MoveToState(JSRAbsoluteLong);
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default: assert(false);
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}
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});
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StdCASE(BTST, {
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switch(instruction_.mode(1)) {
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default:
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@ -651,6 +681,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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StdCASE(MOVEMtoMl, perform_state_ = MOVEMtoM);
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StdCASE(MOVEMtoMw, perform_state_ = MOVEMtoM);
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StdCASE(TSTb, perform_state_ = Perform_np);
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StdCASE(TSTw, perform_state_ = Perform_np);
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StdCASE(TSTl, perform_state_ = Perform_np);
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default:
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assert(false);
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}
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@ -818,6 +852,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRAddressRegisterIndirect):
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effective_address_[0] = registers_[8 + instruction_.reg(next_operand_)].l;
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MoveToState(JSR_push);
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//
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// AddressRegisterIndirectWithPostincrement
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//
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@ -911,6 +949,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRAddressRegisterIndirectWithDisplacement):
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effective_address_[0] =
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registers_[8 + instruction_.reg(next_operand_)].l +
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int16_t(prefetch_.w);
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IdleBus(1); // n
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MoveToState(JSR_push);
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//
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// ProgramCounterIndirectWithDisplacement
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//
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@ -945,6 +990,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRProgramCounterIndirectWithDisplacement):
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effective_address_[0] =
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program_counter_.l - 2 +
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int16_t(prefetch_.w);
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IdleBus(1); // n
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MoveToState(JSR_push);
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//
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// AddressRegisterIndirectWithIndex8bitDisplacement
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//
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@ -981,6 +1033,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRAddressRegisterIndirectWithIndex8bitDisplacement):
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effective_address_[0] = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
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IdleBus(3); // n nn
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MoveToState(JSR_push);
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//
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// ProgramCounterIndirectWithIndex8bitDisplacement
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//
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@ -1010,6 +1067,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRProgramCounterIndirectWithIndex8bitDisplacement):
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effective_address_[0] = d8Xn(program_counter_.l - 2);
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IdleBus(3); // n nn
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MoveToState(JSR_push);
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#undef d8Xn
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//
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@ -1039,6 +1101,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRAbsoluteShort):
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effective_address_[0] = int16_t(prefetch_.w);
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IdleBus(1); // n
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MoveToState(JSR_push);
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//
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// AbsoluteLong
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//
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@ -1071,6 +1138,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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state_ = post_ea_state_;
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break;
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BeginState(JSRAbsoluteLong):
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Prefetch(); // np
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effective_address_[0] = prefetch_.l;
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MoveToState(JSR_push);
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//
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// ImmediateData
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//
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@ -1390,21 +1462,20 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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BeginState(BSR):
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IdleBus(1); // n
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SetupDataAccess(0, Microcycle::SelectWord);
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SetDataAddress(registers_[15].l);
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// Push the next PC to the stack; determine here what
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// the next one should be.
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// Calculate the address of the next instruction.
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if(instruction_.operand_size() == InstructionSet::M68k::DataSize::Word) {
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temporary_address_.l = instruction_address_.l + 4;
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} else {
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temporary_address_.l = instruction_address_.l + 2;
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}
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// Push it to the stack.
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SetupDataAccess(0, Microcycle::SelectWord);
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SetDataAddress(registers_[15].l);
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registers_[15].l -= 4;
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Access(temporary_address_.high); // nS
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registers_[15].l += 2;
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Access(temporary_address_.low); // ns
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Access(temporary_address_.low); // ns
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registers_[15].l -= 2;
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// Get the new PC.
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@ -1415,6 +1486,30 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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MoveToState(Decode);
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//
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// JSR [push only; address calculation elsewhere]
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//
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BeginState(JSR_push):
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// Grab the address of the next instruction.
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temporary_address_.l = program_counter_.l - 4;
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// Update the program counter and prefetch once.
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program_counter_.l = effective_address_[0];
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Prefetch(); // np
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// Push the old PC onto the stack in upper, lower order.
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SetupDataAccess(0, Microcycle::SelectWord);
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SetDataAddress(registers_[15].l);
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registers_[15].l -= 4;
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Access(temporary_address_.high); // nS
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registers_[15].l += 2;
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Access(temporary_address_.low); // ns
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registers_[15].l -= 2;
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// Prefetch once more.
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Prefetch();
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MoveToState(Decode);
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//
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// BSET, BCHG, BCLR
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//
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