From 626e719fabc5b44da69e6d525cb8449d1d0e10e4 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Thu, 3 Nov 2016 22:50:49 -0400 Subject: [PATCH 1/5] Added sanity checks on loading quickly. --- Machines/Oric/Oric.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Machines/Oric/Oric.cpp b/Machines/Oric/Oric.cpp index 05aed5902..13bf6b9c7 100644 --- a/Machines/Oric/Oric.cpp +++ b/Machines/Oric/Oric.cpp @@ -52,7 +52,7 @@ unsigned int Machine::perform_bus_operation(CPU6502::BusOperation operation, uin // 024D = 0 => fast; otherwise slow // E6C9 = read byte: return byte in A - if(address == 0xe6c9 && _use_fast_tape_hack && operation == CPU6502::BusOperation::ReadOpcode) + if(address == 0xe6c9 && _use_fast_tape_hack && operation == CPU6502::BusOperation::ReadOpcode && _via.tape->has_tape() && !_via.tape->get_tape()->is_at_end()) { uint8_t next_byte = _via.tape->get_next_byte(!_ram[0x024d]); set_value_of_register(CPU6502::A, next_byte); From eccfdabeabb4ce147f24e9ca696a50c9896a7663 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Thu, 3 Nov 2016 22:52:02 -0400 Subject: [PATCH 2/5] Temporarily disabled thread hop, until I can find a way to batch these things. --- Outputs/Speaker.hpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Outputs/Speaker.hpp b/Outputs/Speaker.hpp index 918dbe4a6..bceeb1d5b 100644 --- a/Outputs/Speaker.hpp +++ b/Outputs/Speaker.hpp @@ -90,11 +90,12 @@ class Speaker { protected: void enqueue(std::function function) { - _queue->enqueue(function); + function(); +// _queue->enqueue(function); } void flush() { - _queue->flush(); +// _queue->flush(); } std::unique_ptr _buffer_in_progress; From 30c670f8deeefb7c4bf718c1382b8a22b3369d3c Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 4 Nov 2016 21:30:18 -0400 Subject: [PATCH 3/5] Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting. --- Components/6522/6522.hpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Components/6522/6522.hpp b/Components/6522/6522.hpp index 68a3292a1..60fe8073c 100644 --- a/Components/6522/6522.hpp +++ b/Components/6522/6522.hpp @@ -90,7 +90,7 @@ template class MOS6522 { _registers.interrupt_flags &= ~InterruptFlag::Timer1; if(address == 0x05) { - _registers.timer[0] = _registers.timer_latch[0]; + _registers.next_timer[0] = _registers.timer_latch[0]; _timer_is_running[0] = true; } reevaluate_interrupts(); @@ -100,7 +100,7 @@ template class MOS6522 { case 0x8: _registers.timer_latch[1] = value; break; case 0x9: _registers.interrupt_flags &= ~InterruptFlag::Timer2; - _registers.timer[1] = _registers.timer_latch[1] | (uint16_t)(value << 8); + _registers.next_timer[1] = _registers.timer_latch[1] | (uint16_t)(value << 8); _timer_is_running[1] = true; reevaluate_interrupts(); break; @@ -242,7 +242,9 @@ template class MOS6522 { else\ _registers.timer[0] --;\ \ - _registers.timer[1] --; + _registers.timer[1] --; \ + if(_registers.next_timer[0] >= 0) { _registers.timer[0] = _registers.next_timer[0]; _registers.next_timer[0] = -1; }\ + if(_registers.next_timer[1] >= 0) { _registers.timer[1] = _registers.next_timer[1]; _registers.next_timer[1] = -1; }\ // IRQ is raised on the half cycle after overflow #define phase1() \ @@ -367,6 +369,7 @@ template class MOS6522 { struct Registers { uint8_t output[2], input[2], data_direction[2]; uint16_t timer[2], timer_latch[2], last_timer[2]; + int next_timer[2]; uint8_t shift; uint8_t auxiliary_control, peripheral_control; uint8_t interrupt_flags, interrupt_enable; @@ -377,7 +380,8 @@ template class MOS6522 { output{0, 0}, input{0, 0}, data_direction{0, 0}, auxiliary_control(0), peripheral_control(0), interrupt_flags(0), interrupt_enable(0), - last_timer{0, 0}, timer_needs_reload(false) {} + last_timer{0, 0}, timer_needs_reload(false), + next_timer{-1, -1} {} } _registers; // control state From fa65cc2058cbf1bf3f13a4280d963cf12f4c3fd7 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sat, 5 Nov 2016 12:57:01 -0400 Subject: [PATCH 4/5] Resolved type conversion error. --- Components/6522/6522.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Components/6522/6522.hpp b/Components/6522/6522.hpp index 60fe8073c..4660d75f7 100644 --- a/Components/6522/6522.hpp +++ b/Components/6522/6522.hpp @@ -243,8 +243,8 @@ template class MOS6522 { _registers.timer[0] --;\ \ _registers.timer[1] --; \ - if(_registers.next_timer[0] >= 0) { _registers.timer[0] = _registers.next_timer[0]; _registers.next_timer[0] = -1; }\ - if(_registers.next_timer[1] >= 0) { _registers.timer[1] = _registers.next_timer[1]; _registers.next_timer[1] = -1; }\ + if(_registers.next_timer[0] >= 0) { _registers.timer[0] = (uint16_t)_registers.next_timer[0]; _registers.next_timer[0] = -1; }\ + if(_registers.next_timer[1] >= 0) { _registers.timer[1] = (uint16_t)_registers.next_timer[1]; _registers.next_timer[1] = -1; }\ // IRQ is raised on the half cycle after overflow #define phase1() \ From dda0c8af306138801746f5773cb4c4f90755cfff Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sat, 5 Nov 2016 12:58:56 -0400 Subject: [PATCH 5/5] Fixed tests. --- OSBindings/Mac/Clock SignalTests/6522Tests.swift | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/OSBindings/Mac/Clock SignalTests/6522Tests.swift b/OSBindings/Mac/Clock SignalTests/6522Tests.swift index 8515286e5..f82c51610 100644 --- a/OSBindings/Mac/Clock SignalTests/6522Tests.swift +++ b/OSBindings/Mac/Clock SignalTests/6522Tests.swift @@ -24,6 +24,9 @@ class MOS6522Tests: XCTestCase { $0.setValue(10, forRegister: 4) $0.setValue(0, forRegister: 5) + // complete the setting cycle + $0.run(forHalfCycles: 2) + // run for 5 cycles $0.run(forHalfCycles: 10) @@ -42,6 +45,9 @@ class MOS6522Tests: XCTestCase { // change the low-byte latch $0.setValue(0x40, forRegister: 8) + // complete the cycle + $0.run(forHalfCycles: 2) + // chek that the new latched value hasn't been copied XCTAssert($0.value(forRegister: 8) == 0x10, "Low order byte should be 0x10; was \($0.value(forRegister: 8))") XCTAssert($0.value(forRegister: 9) == 0x20, "High order byte should be 0x20; was \($0.value(forRegister: 9))") @@ -49,6 +55,9 @@ class MOS6522Tests: XCTestCase { // write the low-byte latch $0.setValue(0x50, forRegister: 9) + // complete the cycle + $0.run(forHalfCycles: 2) + // chek that the latched value has been copied XCTAssert($0.value(forRegister: 8) == 0x40, "Low order byte should be 0x50; was \($0.value(forRegister: 8))") XCTAssert($0.value(forRegister: 9) == 0x50, "High order byte should be 0x40; was \($0.value(forRegister: 9))") @@ -63,6 +72,9 @@ class MOS6522Tests: XCTestCase { $0.setValue(0x40, forRegister: 11) $0.setValue(0x40 | 0x80, forRegister: 14) + // complete the cycle to set initial values + $0.run(forHalfCycles: 2) + // run for 16 cycles $0.run(forHalfCycles: 32) @@ -103,6 +115,9 @@ class MOS6522Tests: XCTestCase { // ask to output 0x8c $0.setValue(0x8c, forRegister: 0) + // complete the cycle + $0.run(forHalfCycles: 2) + // set current input as 0xda $0.portBInput = 0xda