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https://github.com/TomHarte/CLK.git
synced 2024-11-23 03:32:32 +00:00
Pulled vertical sync detection entirely outside the loop, and gave it greater perspective.
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@ -34,9 +34,10 @@ void CRT::set_new_timing(unsigned int cycles_per_line, unsigned int height_of_di
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colour_cycle_numerator_ = colour_cycle_numerator;
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phase_alternates_ = should_alternate;
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is_alernate_line_ &= phase_alternates_;
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cycles_per_line_ = cycles_per_line;
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unsigned int multiplied_cycles_per_line = cycles_per_line * time_multiplier_;
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// generate timing values implied by the given arbuments
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// generate timing values implied by the given arguments
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sync_capacitor_charge_threshold_ = ((int)(syncCapacityLineChargeThreshold * cycles_per_line) * 3) / 4;
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// create the two flywheels
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@ -265,16 +266,30 @@ void CRT::advance_cycles(unsigned int number_of_cycles, bool hsync_requested, bo
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void CRT::output_scan(const Scan *const scan)
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{
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const bool this_is_sync = (scan->type == Scan::Type::Sync);
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const bool is_trailing_edge = (is_receiving_sync_ && !this_is_sync);
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const bool is_leading_edge = (!is_receiving_sync_ && this_is_sync);
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is_receiving_sync_ = this_is_sync;
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// Accumulate: (i) a total of the amount of time in sync; and (ii) the amount of time since sync.
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if(this_is_sync) { cycles_of_sync_ += scan->number_of_cycles; cycles_since_sync_ = 0; }
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else cycles_since_sync_ += scan->number_of_cycles;
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bool vsync_requested = false;
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// If it has been at least half a line since sync ended, then it is safe to decide whether what ended
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// was vertical sync.
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if(cycles_since_sync_ > (cycles_per_line_ >> 1))
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{
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// If it was vertical sync, set that flag. If it wasn't, clear the summed amount of sync to avoid
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// a mistaken vertical sync due to an aggregate of horizontals.
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vsync_requested = (cycles_of_sync_ > sync_capacitor_charge_threshold_);
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if(vsync_requested || cycles_of_sync_ < (cycles_per_line_ >> 2))
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cycles_of_sync_ = 0;
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}
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// This introduces a blackout period close to the expected vertical sync point in which horizontal syncs are not
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// recognised, effectively causing the horizontal flywheel to freewheel during that period. This attempts to seek
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// the problem that vertical sync otherwise often starts halfway through a scanline, which confuses the horizontal
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// flywheel. I'm currently unclear whether this is an accurate solution to this problem.
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const bool hsync_requested = is_leading_edge && !vertical_flywheel_->is_near_expected_sync();
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const bool vsync_requested = is_trailing_edge && (sync_capacitor_charge_level_ >= sync_capacitor_charge_threshold_);
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// simplified colour burst logic: if it's within the back porch we'll take it
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if(scan->type == Scan::Type::ColourBurst)
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@ -293,12 +308,6 @@ void CRT::output_scan(const Scan *const scan)
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sync_period_ = is_receiving_sync_ ? (sync_period_ + scan->number_of_cycles) : 0;
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advance_cycles(scan->number_of_cycles, hsync_requested, vsync_requested, scan->type);
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// either charge or deplete the vertical retrace capacitor (making sure it stops at 0)
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if(this_is_sync)
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sync_capacitor_charge_level_ += scan->number_of_cycles;
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else
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sync_capacitor_charge_level_ = std::max(sync_capacitor_charge_level_ - (int)scan->number_of_cycles, 0);
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}
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/*
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@ -94,6 +94,11 @@ class CRT {
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enqueued_openGL_functions_.push_back(function);
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}
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// sync counter, for determining vertical sync
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unsigned int cycles_of_sync_;
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unsigned int cycles_since_sync_;
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unsigned int cycles_per_line_;
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public:
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/*! Constructs the CRT with a specified clock rate, height and colour subcarrier frequency.
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The requested number of buffers, each with the requested number of bytes per pixel,
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