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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-25 11:17:26 +00:00

Some data is marginally reaching the CPU from the tape.

This commit is contained in:
Thomas Harte
2016-01-19 22:05:34 -05:00
parent 832797182f
commit e65cd4cf06
9 changed files with 184 additions and 37 deletions
+23 -5
View File
@@ -16,14 +16,21 @@ namespace SignalProcessing {
class Stepper
{
public:
Stepper(uint64_t output_rate, uint64_t update_rate)
Stepper()
{
whole_step_ = output_rate / update_rate;
adjustment_up_ = (int64_t)(output_rate % update_rate) << 1;
adjustment_down_ = (int64_t)update_rate << 1;
Stepper(1, 1);
}
inline uint64_t update()
Stepper(uint64_t output_rate, uint64_t input_rate)
{
input_rate_ = input_rate;
output_rate_ = output_rate;
whole_step_ = output_rate / input_rate;
adjustment_up_ = (int64_t)(output_rate % input_rate) << 1;
adjustment_down_ = (int64_t)input_rate << 1;
}
inline uint64_t step()
{
uint64_t update = whole_step_;
accumulated_error_ += adjustment_up_;
@@ -35,10 +42,21 @@ class Stepper
return update;
}
inline uint64_t get_output_rate()
{
return output_rate_;
}
inline uint64_t get_input_rate()
{
return input_rate_;
}
private:
uint64_t whole_step_;
int64_t adjustment_up_, adjustment_down_;
int64_t accumulated_error_;
uint64_t input_rate_, output_rate_;
};
}