6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-10 16:30:07 +00:00
Code Issues Projects Releases Wiki Activity

Introduce further default state.

Browse Source
This commit is contained in:
Thomas Harte 2021-04-24 23:18:00 -04:00
parent d61f478a39
commit e7a9ae18a1
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
Processors/Z80/State/State.hpp
View File

@ -60,25 +60,25 @@ struct State: public Reflection::StructImpl<State> {
obviously doesn't. obviously doesn't.
*/ */
struct ExecutionState: public Reflection::StructImpl<ExecutionState> { struct ExecutionState: public Reflection::StructImpl<ExecutionState> {
bool is_halted; bool is_halted = false;
uint8_t requests; uint8_t requests = 0;
uint8_t last_requests; uint8_t last_requests = 0;
uint8_t temp8; uint8_t temp8 = 0;
uint8_t operation; uint8_t operation = 0;
uint16_t temp16; uint16_t temp16 = 0;
unsigned int flag_adjustment_history; unsigned int flag_adjustment_history = 0;
uint16_t pc_increment; uint16_t pc_increment = 1;
uint16_t refresh_address; uint16_t refresh_address = 0;
ReflectableEnum(Phase, ReflectableEnum(Phase,
UntakenConditionalCall, Reset, IRQMode0, IRQMode1, IRQMode2, UntakenConditionalCall, Reset, IRQMode0, IRQMode1, IRQMode2,
NMI, FetchDecode, Operation NMI, FetchDecode, Operation
); );
Phase phase; Phase phase = Phase::FetchDecode;
int half_cycles_into_step; int half_cycles_into_step = 0;
int steps_into_phase; int steps_into_phase = 0;
uint16_t instruction_page = 0; uint16_t instruction_page = 0;
ExecutionState(); ExecutionState();