mirror of
https://github.com/TomHarte/CLK.git
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Start shuffling parameters into conventional order; expand on cmp–cmpli, dcbf–dcbz.
This commit is contained in:
Thomas Harte
parent
a3b110aee5
commit
e83267751e
@ -73,7 +73,7 @@ enum class Operation: uint8_t {
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/// Absolute.
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/// abs abs. abso abso.
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/// rA(), rD(), oe()
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/// rD(), rA() [oe(), rc()]
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///
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/// |rA| is placed into rD. If rA = 0x8000'0000 then 0x8000'0000 is placed into rD
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/// and XER[OV] is set if oe() indicates that overflow is enabled.
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@ -81,7 +81,7 @@ enum class Operation: uint8_t {
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/// Cache line compute size.
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/// clcs
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/// rA(), rD()
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/// rD(), rA()
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///
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/// The size of the cache line specified by rA is placed into rD. Cf. the CacheLine enum.
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/// As an aside: all cache lines are 64 bytes on the MPC601.
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@ -89,7 +89,7 @@ enum class Operation: uint8_t {
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/// Divide.
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/// div div. divo divo.
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/// rA(), rB(), rD(), rc(), oe()
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/// rD(), rA(), rB() [rc(), oe()]
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///
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/// Unsigned 64-bit divide. rA|MQ / rB is placed into rD and the
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/// remainder is placed into MQ. The ermainder has the same sign as the dividend
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@ -141,14 +141,14 @@ enum class Operation: uint8_t {
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/// Add.
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/// add add. addo addo.
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/// rA(), rB(), rD(), rc(), oe()
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/// rD(), rA(), rB() [rc(), oe()]
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///
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/// rD() = rA() + rB(). Carry is ignored, rD() may be equal to rA() or rB().
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addx,
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/// Add carrying.
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/// addc addc. addco addco.
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/// rA(), rB(), rD(), rc(), oe()
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/// rD(), rA(), rB() [rc(), oe()]
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///
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/// rD() = rA() + rB().
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/// XER[CA] is updated with carry; if oe() is set then so are XER[SO] and XER[OV].
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@ -157,7 +157,7 @@ enum class Operation: uint8_t {
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/// Add extended.
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/// adde adde. addeo addeo.
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/// rA(), rB(), rD(), rc(), eo()
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/// rD(), rA(), rB() [rc(), eo()]
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///
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/// rD() = rA() + rB() + XER[CA]; XER[CA] is set if further carry occurs.
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/// oe() and rc() apply.
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@ -165,14 +165,14 @@ enum class Operation: uint8_t {
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/// Add immediate.
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/// addi
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/// rA(), rD(), simm()
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/// rD(), rA(), simm()
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///
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/// rD() = (rA() | 0) + simm()
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addi,
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/// Add immediate carrying.
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/// addic
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/// rA(), rD(), simm()
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/// rD(), rA(), simm()
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] is updated.
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@ -180,7 +180,7 @@ enum class Operation: uint8_t {
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/// Add immediate carrying and record.
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/// addic.
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/// rA(), rD(), simm()
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/// rD(), rA(), simm()
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///
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/// rD() = (rA() | 0) + simm()
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/// XER[CA] and the condition register are updated.
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@ -188,48 +188,48 @@ enum class Operation: uint8_t {
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/// Add immediate shifted.
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/// addis.
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/// rA(), rD(), simm()
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/// rD(), rA(), simm()
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///
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/// rD() = (rA() | 0) + (simm() << 16)
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addis,
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/// Add to minus one.
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/// addme addme. addmeo addmeo.
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/// rA(), rD(), rc(), oe()
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/// rD(), rA() [rc(), oe()]
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///
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/// rD() = rA() + XER[CA] + 0xffff'ffff
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addmex,
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/// Add to zero extended.
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/// addze addze. addzeo addzeo.
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/// rA(), rD(), rc(), oe()
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/// rD(), rA() [rc(), oe()]
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///
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/// rD() = rA() + XER[CA]
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addzex,
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/// And.
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/// and, and.
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/// rA(), rB(), rD(), rc()
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/// rA(), rS(), rB() [rc()]
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andx,
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/// And with complement.
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/// andc, andc.
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/// rA(), rB(), rD(), rc()
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/// rA(), rS(), rB() [rc()]
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andcx,
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/// And immediate.
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/// andi.
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/// rA(), rD(), uimm()
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/// rA(), rS(), uimm()
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andi_,
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/// And immediate shifted.
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/// andis.
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/// rA(), rD(), uimm()
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/// rA(), rS(), uimm()
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andis_,
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/// Branch unconditional.
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/// b bl ba bla
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/// aa(), li(), lk()
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/// li() [aa(), lk()]
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///
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/// Use li() to get the included immediate value.
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///
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@ -239,7 +239,7 @@ enum class Operation: uint8_t {
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/// Branch conditional.
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/// bne bne+ beq bdnzt+ bdnzf bdnzt bdnzfla ...
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/// aa(), lk(), bd(), bi(), bo()
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/// bo(), bi(), bd() [aa(), lk()]
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///
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/// aa() determines whether the branch has a relative or absolute target.
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/// lk() determines whether to update the link register.
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@ -250,7 +250,7 @@ enum class Operation: uint8_t {
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/// Branch conditional to count register.
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/// bctr bctrl bnectrl bnectrl bltctr blectr ...
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/// aa(), lk(), bi(), bo()
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/// bo(), bi() [aa(), lk()]
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///
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/// aa(), bi(), bo() and lk() are as per bcx.
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///
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@ -260,56 +260,102 @@ enum class Operation: uint8_t {
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/// Branch conditional to link register.
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/// blr blrl bltlr blelrl bnelrl ...
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/// aa(), lk(), bi(), bo()
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/// bo(), bi() [aa(), lk()]
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///
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/// aa(), bi(), bo() and lk() are as per bcx.
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bclrx,
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cmp, cmpi, cmpl, cmpli,
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/// Compare
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/// cmp
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/// crfD(), l(), rA(), rB()
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cmp,
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/// Compare immediate.
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/// cmpi
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/// crfD(), l(), rA(), simm()
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cmpi,
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/// Compare logical.
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/// cmpl
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/// crfD(), l(), rA(), rB()
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cmpl,
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/// Compare logical immediate.
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/// cmpli
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/// crfD(), l(), rA(), uimm()
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cmpli,
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/// Count leading zero words.
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/// cntlzw cntlzw.
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/// rA(), rS() [rc()]
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cntlzwx,
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/// Condition register and.
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/// crand
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crand,
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/// Condition register and with complement.
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/// crandc
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crandc,
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/// Condition register equivalent.
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/// creqv
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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creqv,
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/// Condition register nand.
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/// crnand
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crnand,
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/// Condition register nor.
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/// crnor
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crnor,
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/// Condition register or.
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/// cror
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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cror,
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/// Condition register or with complement.
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/// crorc
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crorc,
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/// Condition register xor.
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/// crxor
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/// crbA(), crbB(), crbD()
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/// crbD(), crbA(), crbB()
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crxor,
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/// Data cache block flush.
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/// dcbf
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/// rA(), rB()
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dcbf,
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dcbst, dcbt, dcbtst, dcbz, divwx, divwux, eciwx, ecowx, eieio, eqvx,
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/// Data cache block store.
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/// dcbst
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/// rA(), rB()
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dcbst,
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/// Data cache block touch.
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/// dcbt
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/// rA(), rB()
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dcbt,
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/// Data cache block touch for store.
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/// dcbtst
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/// rA(), rB()
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dcbtst,
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/// Data cache block set to zero.
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/// dcbz
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/// rA(), rB()
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dcbz,
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divwx, divwux, eciwx, ecowx, eieio, eqvx,
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extsbx, extshx, fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx,
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fdivx, fdivsx, fmaddx, fmaddsx, fmrx, fmsubx, fmsubsx, fmulx, fmulsx,
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fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx,
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@ -437,7 +483,12 @@ enum class Operation: uint8_t {
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/// rA(), rB(), rS(), mb(), me(), rc()
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rlwnmx,
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sc, slwx, srawx, srawix, srwx, stb, stbu,
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sc,
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/// Shift left word.
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/// slw slw.
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/// rA(), rS(), rB() [rc()]
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slwx, srawx, srawix, srwx, stb, stbu,
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/// Store byte with update indexed.
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///
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@ -507,6 +558,10 @@ enum class Operation: uint8_t {
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//
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// MARK: - 32-bit, supervisor level.
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//
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/// Data cache block invalidate.
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/// dcbi
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/// rA(), rB()
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dcbi,
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//
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