mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-28 21:49:27 +00:00
Sketches out a blitter class.
This commit is contained in:
Thomas Harte
parent
b3d55cc16d
commit
e85db40b0f
@ -24,6 +24,8 @@
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#define LOG_PREFIX "[Amiga] "
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#include "../../Outputs/Log.hpp"
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#include "Blitter.hpp"
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namespace Amiga {
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class ConcreteMachine:
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@ -35,6 +37,7 @@ class ConcreteMachine:
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public:
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ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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blitter_(reinterpret_cast<uint16_t *>(memory_.chip_ram.data()), memory_.chip_ram.size()),
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cia_a_handler_(memory_),
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cia_a_(cia_a_handler_),
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cia_b_(cia_b_handler_)
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@ -48,7 +51,7 @@ class ConcreteMachine:
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if(!request.validate(roms)) {
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throw ROMMachine::Error::MissingROMs;
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}
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Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart_.data());
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Memory::PackBigEndian16(roms.find(rom_name)->second, memory_.kickstart.data());
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// NTSC clock rate: 2*3.579545 = 7.15909Mhz.
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// PAL clock rate: 7.09379Mhz.
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@ -88,7 +91,7 @@ class ConcreteMachine:
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// printf("%06x\n", *cycle.address);
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// }
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if(!memory_.regions_[address >> 18].read_write_mask) {
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if(!memory_.regions[address >> 18].read_write_mask) {
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if((cycle.operation & (Microcycle::SelectByte | Microcycle::SelectWord))) {
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// Check for various potential chip accesses.
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@ -155,6 +158,10 @@ class ConcreteMachine:
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break;
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// DMA management.
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case Read(0x002):
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LOG("DMA control and status read");
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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case Write(0x096):
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ApplySetClear(dma_control_);
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LOG("DMA control modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{dma_control_});
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@ -199,6 +206,34 @@ class ConcreteMachine:
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cycle.set_value16(0xffff);
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break;
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// Blitter.
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case Write(0x040): blitter_.set_control(0, cycle.value16()); break;
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case Write(0x042): blitter_.set_control(1, cycle.value16()); break;
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case Write(0x044): blitter_.set_first_word_mask(cycle.value16()); break;
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case Write(0x046): blitter_.set_last_word_mask(cycle.value16()); break;
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case Write(0x048): blitter_.set_pointer(2, 16, cycle.value16()); break;
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case Write(0x04a): blitter_.set_pointer(2, 0, cycle.value16()); break;
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case Write(0x04c): blitter_.set_pointer(1, 16, cycle.value16()); break;
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case Write(0x04e): blitter_.set_pointer(1, 0, cycle.value16()); break;
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case Write(0x050): blitter_.set_pointer(0, 16, cycle.value16()); break;
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case Write(0x052): blitter_.set_pointer(0, 0, cycle.value16()); break;
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case Write(0x054): blitter_.set_pointer(3, 16, cycle.value16()); break;
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case Write(0x056): blitter_.set_pointer(3, 0, cycle.value16()); break;
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case Write(0x058): blitter_.set_size(cycle.value16()); break;
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case Write(0x05a): blitter_.set_minterms(cycle.value16()); break;
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case Write(0x05c): blitter_.set_vertical_size(cycle.value16()); break;
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case Write(0x05e): blitter_.set_horizontal_size(cycle.value16()); break;
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case Write(0x060): blitter_.set_modulo(2, cycle.value16()); break;
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case Write(0x062): blitter_.set_modulo(1, cycle.value16()); break;
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case Write(0x064): blitter_.set_modulo(0, cycle.value16()); break;
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case Write(0x066): blitter_.set_modulo(3, cycle.value16()); break;
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case Write(0x070): blitter_.set_data(2, cycle.value16()); break;
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case Write(0x072): blitter_.set_data(1, cycle.value16()); break;
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case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
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// Colour palette.
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case Write(0x180): case Write(0x182): case Write(0x184): case Write(0x186):
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@ -229,8 +264,8 @@ class ConcreteMachine:
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} else {
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// A regular memory access.
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cycle.apply(
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&memory_.regions_[address >> 18].contents[address],
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memory_.regions_[address >> 18].read_write_mask
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&memory_.regions[address >> 18].contents[address],
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memory_.regions[address >> 18].read_write_mask
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);
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}
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@ -243,13 +278,13 @@ class ConcreteMachine:
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// MARK: - Memory map.
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> ram_{};
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std::array<uint8_t, 512*1024> kickstart_{0xff};
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std::array<uint8_t, 512*1024> chip_ram{};
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std::array<uint8_t, 512*1024> kickstart{0xff};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions_[64]; // i.e. top six bits are used as an index.
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} regions[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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@ -267,7 +302,7 @@ class ConcreteMachine:
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart_.data(), CPU::MC68000::Microcycle::PermitRead);
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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@ -282,13 +317,10 @@ class ConcreteMachine:
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart_.data(), CPU::MC68000::Microcycle::PermitRead);
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set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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// Mirror RAM to fill out the address range up to $20'0000 (?)
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set_region(0x00'0000, 0x08'0000, ram_.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x08'0000, 0x10'0000, ram_.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x10'0000, 0x18'0000, ram_.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x18'0000, 0x20'0000, ram_.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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@ -301,8 +333,8 @@ class ConcreteMachine:
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base -= start;
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for(int c = start >> 18; c < end >> 18; c++) {
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regions_[c].contents = base;
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regions_[c].read_write_mask = read_write_mask;
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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} memory_;
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@ -316,9 +348,10 @@ class ConcreteMachine:
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// TODO.
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}
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// MARK: - DMA control.
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// MARK: - DMA control, blitter and Paula.
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uint16_t dma_control_ = 0;
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Blitter blitter_;
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// MARK: - CIAs.
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69
Machines/Amiga/Blitter.cpp
Normal file
69
Machines/Amiga/Blitter.cpp
Normal file
@ -0,0 +1,69 @@
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//
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// Blitter.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#include "Blitter.hpp"
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//#define NDEBUG
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#define LOG_PREFIX "[Blitter] "
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#include "../../Outputs/Log.hpp"
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using namespace Amiga;
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Blitter::Blitter(uint16_t *ram, size_t size) : ram_(ram), ram_size_(size) {}
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void Blitter::set_control(int index, uint16_t value) {
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LOG("Set control " << index << " to " << PADHEX(4) << value);
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}
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void Blitter::set_first_word_mask(uint16_t value) {
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LOG("Set first word mask: " << PADHEX(4) << value);
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}
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void Blitter::set_last_word_mask(uint16_t value) {
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LOG("Set last word mask: " << PADHEX(4) << value);
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}
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void Blitter::set_pointer(int channel, int shift, uint16_t value) {
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LOG("Set pointer " << channel << " shift " << shift << " to " << PADHEX(4) << value);
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}
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void Blitter::set_size(uint16_t value) {
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LOG("Set size " << PADHEX(4) << value);
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}
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void Blitter::set_minterms(uint16_t value) {
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LOG("Set minterms " << PADHEX(4) << value);
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}
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void Blitter::set_vertical_size(uint16_t value) {
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LOG("Set vertical size " << PADHEX(4) << value);
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}
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void Blitter::set_horizontal_size(uint16_t value) {
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LOG("Set horizontal size " << PADHEX(4) << value);
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}
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void Blitter::set_modulo(int channel, uint16_t value) {
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LOG("Set modulo size " << channel << " to " << PADHEX(4) << value);
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}
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void Blitter::set_data(int channel, uint16_t value) {
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LOG("Set data " << channel << " to " << PADHEX(4) << value);
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}
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uint16_t Blitter::get_status() {
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LOG("Returned dummy status");
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return 0;
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}
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Cycles Blitter::get_remaining_cycles() {
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return Cycles(0);
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}
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void Blitter::run_for(Cycles) {
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}
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55
Machines/Amiga/Blitter.hpp
Normal file
55
Machines/Amiga/Blitter.hpp
Normal file
@ -0,0 +1,55 @@
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//
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// Blitter.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 22/07/2021.
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// Copyright © 2021 Thomas Harte. All rights reserved.
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//
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#ifndef Blitter_hpp
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#define Blitter_hpp
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#include <cstddef>
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#include <cstdint>
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#include "../../ClockReceiver/ClockReceiver.hpp"
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namespace Amiga {
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class Blitter {
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public:
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Blitter(uint16_t *ram, size_t size);
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// Various setters; it's assumed that address decoding is handled externally.
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//
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// In all cases where a channel is identified numerically, it's taken that
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// 0 = A, 1 = B, 2 = C, 3 = D.
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void set_control(int index, uint16_t value);
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void set_first_word_mask(uint16_t value);
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void set_last_word_mask(uint16_t value);
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void set_pointer(int channel, int shift, uint16_t value);
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void set_size(uint16_t value);
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void set_minterms(uint16_t value);
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void set_vertical_size(uint16_t value);
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void set_horizontal_size(uint16_t value);
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void set_modulo(int channel, uint16_t value);
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void set_data(int channel, uint16_t value);
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uint16_t get_status();
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/// @returns The number of 'cycles' required to complete the current
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/// operation, if any, or Cycles(0) if no operation is pending.
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Cycles get_remaining_cycles();
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/// Advances the stated number of cycles.
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void run_for(Cycles);
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private:
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uint16_t *const ram_;
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const size_t ram_size_;
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};
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}
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#endif /* Blitter_hpp */
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@ -580,6 +580,8 @@
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4B9D0C4B22C7D70A00DE1AD3 /* 68000BCDTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B9D0C4A22C7D70900DE1AD3 /* 68000BCDTests.mm */; };
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4B9D0C4D22C7DA1A00DE1AD3 /* 68000ControlFlowTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B9D0C4C22C7DA1A00DE1AD3 /* 68000ControlFlowTests.mm */; };
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4B9D0C4F22C7E0CF00DE1AD3 /* 68000RollShiftTests.mm in Sources */ = {isa = PBXBuildFile; fileRef = 4B9D0C4E22C7E0CF00DE1AD3 /* 68000RollShiftTests.mm */; };
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4B9EC0E226AA27BA0060A31F /* Blitter.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B9EC0E126AA27BA0060A31F /* Blitter.cpp */; };
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4B9EC0E326AA27BA0060A31F /* Blitter.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B9EC0E126AA27BA0060A31F /* Blitter.cpp */; };
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4B9F11C92272375400701480 /* qltrace.txt.gz in Resources */ = {isa = PBXBuildFile; fileRef = 4B9F11C82272375400701480 /* qltrace.txt.gz */; };
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4B9F11CA2272433900701480 /* libz.tbd in Frameworks */ = {isa = PBXBuildFile; fileRef = 4B69FB451C4D950F00B5F0AA /* libz.tbd */; };
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4B9F11CC22729B3600701480 /* OPCLOGR2.BIN in Resources */ = {isa = PBXBuildFile; fileRef = 4B9F11CB22729B3500701480 /* OPCLOGR2.BIN */; };
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@ -1584,6 +1586,8 @@
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4B9D0C4A22C7D70900DE1AD3 /* 68000BCDTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = 68000BCDTests.mm; sourceTree = "<group>"; };
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4B9D0C4C22C7DA1A00DE1AD3 /* 68000ControlFlowTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = 68000ControlFlowTests.mm; sourceTree = "<group>"; };
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4B9D0C4E22C7E0CF00DE1AD3 /* 68000RollShiftTests.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = 68000RollShiftTests.mm; sourceTree = "<group>"; };
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4B9EC0E026AA260C0060A31F /* Blitter.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Blitter.hpp; sourceTree = "<group>"; };
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4B9EC0E126AA27BA0060A31F /* Blitter.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Blitter.cpp; sourceTree = "<group>"; };
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4B9F11C82272375400701480 /* qltrace.txt.gz */ = {isa = PBXFileReference; lastKnownFileType = archive.gzip; path = qltrace.txt.gz; sourceTree = "<group>"; };
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4B9F11CB22729B3500701480 /* OPCLOGR2.BIN */ = {isa = PBXFileReference; lastKnownFileType = archive.macbinary; name = OPCLOGR2.BIN; path = "68000 Coverage/OPCLOGR2.BIN"; sourceTree = "<group>"; };
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4BA0F68C1EEA0E8400E9489E /* ZX8081.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = ZX8081.cpp; sourceTree = "<group>"; };
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@ -4266,6 +4270,8 @@
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children = (
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4BC080D726A25ADA00D03FD8 /* Amiga.hpp */,
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4BC080D826A25ADA00D03FD8 /* Amiga.cpp */,
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4B9EC0E026AA260C0060A31F /* Blitter.hpp */,
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4B9EC0E126AA27BA0060A31F /* Blitter.cpp */,
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);
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path = Amiga;
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sourceTree = "<group>";
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@ -5358,6 +5364,7 @@
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4BF437EF209D0F7E008CBD6B /* SegmentParser.cpp in Sources */,
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4B055AD11FAE9B030060FFFF /* Video.cpp in Sources */,
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4BB4BFBA22A4372F0069048D /* StaticAnalyser.cpp in Sources */,
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||||
4B9EC0E326AA27BA0060A31F /* Blitter.cpp in Sources */,
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||||
4B055AA21FAE85DA0060FFFF /* SSD.cpp in Sources */,
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||||
4B2E86E325DC95150024F1E9 /* Joystick.cpp in Sources */,
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4BEBFB4E2002C4BF000708CC /* FAT12.cpp in Sources */,
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@ -5681,6 +5688,7 @@
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4BCA6CC81D9DD9F000C2D7B2 /* CommodoreROM.cpp in Sources */,
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||||
4BC1317A2346DF2B00E4FF3D /* MSA.cpp in Sources */,
|
||||
4BEBFB4D2002C4BF000708CC /* FAT12.cpp in Sources */,
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||||
4B9EC0E226AA27BA0060A31F /* Blitter.cpp in Sources */,
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||||
4BBFBB6C1EE8401E00C01E7A /* ZX8081.cpp in Sources */,
|
||||
4B83348A1F5DB94B0097E338 /* IRQDelegatePortHandler.cpp in Sources */,
|
||||
4B8DD3862634D37E00B3C866 /* SNA.cpp in Sources */,
|
||||
|
||||
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