mirror of
https://github.com/TomHarte/CLK.git
synced 2026-04-25 11:17:26 +00:00
Reformulate to be slightly more conditional, but substantially deduplicate code.
This commit is contained in:
Thomas Harte
@@ -25,7 +25,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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Storage::cycles_ += cycles;
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if(Storage::cycles_ <= Cycles(0)) return;
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#define restore_point() (__COUNTER__ + int(ResumePoint::Max) + int(AccessProgram::Max))
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#define restore_point() (__COUNTER__ + int(ResumePoint::Max) + int(AddressingMode::Max))
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#define join(a, b) a##b
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#define attach(a, b) join(a, b)
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@@ -55,7 +55,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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Storage::cycles_ -= Storage::bus_handler_.template perform<type>(addr, value); \
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}
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#define access_program(name) int(ResumePoint::Max) + int(AccessProgram::name)
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#define access_program(name) int(ResumePoint::Max) + int(AddressingMode::name)
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using ResumePoint = Storage::ResumePoint;
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using InterruptRequest = Storage::Inputs::InterruptRequest;
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@@ -113,6 +113,56 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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default:
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__builtin_unreachable();
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// MARK: - Read, write or modify accesses.
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access_zero:
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if(Storage::decoded_.type == Type::Write) {
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goto access_zero_write;
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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if(Storage::decoded_.type == Type::Read) {
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perform_operation();
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goto fetch_decode;
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}
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// Modify stall.
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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// Write.
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access_zero_write:
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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access_absolute:
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if(Storage::decoded_.type == Type::Write) {
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goto access_absolute_write;
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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if(Storage::decoded_.type == Type::Read) {
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perform_operation();
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goto fetch_decode;
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}
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// Modify stall.
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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// Write.
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access_absolute_write:
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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// MARK: - Fetch/decode.
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fetch_decode:
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@@ -134,7 +184,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Literal(registers.pc.full), Storage::operand_);
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Storage::decoded_ = Decoder<model>::decode(Storage::opcode_);
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Storage::resume_point_ = ResumePoint::Max + int(Storage::decoded_.program);
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Storage::resume_point_ = ResumePoint::Max + int(Storage::decoded_.mode);
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break;
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// MARK: - Immediate, Implied, Accumulator.
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@@ -156,6 +206,21 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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);
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goto fetch_decode;
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// MARK: - Stack.
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case access_program(Pull):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(Push):
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Stack(registers.dec_s()), Storage::operand_);
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goto fetch_decode;
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// MARK: - Relative.
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case access_program(Relative):
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@@ -180,361 +245,70 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// MARK: - Zero.
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case access_program(ZeroRead):
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case access_program(Zero):
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++registers.pc.full;
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(ZeroWrite):
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++registers.pc.full;
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check_interrupt();
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Storage::address_.halves.low = Storage::operand_;
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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case access_program(ZeroModify):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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goto access_zero;
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// MARK: - Zero indexed.
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case access_program(ZeroXRead):
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case access_program(ZeroIndexed):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(ZeroYRead):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.y;
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(ZeroXWrite):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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check_interrupt();
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Storage::address_.halves.low = Storage::operand_;
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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case access_program(ZeroYWrite):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.y;
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check_interrupt();
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Storage::address_.halves.low = Storage::operand_;
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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case access_program(ZeroXModify):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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case access_program(ZeroYModify):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.y;
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Storage::address_.halves.low += Storage::decoded_.index == Index::X ? registers.x : registers.y;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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goto fetch_decode;
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goto access_zero;
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// MARK: - Absolute.
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case access_program(AbsoluteRead):
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case access_program(Absolute):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(AbsoluteWrite):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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case access_program(AbsoluteModify):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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goto access_absolute;
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// MARK: - Absolute indexed.
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case access_program(AbsoluteXRead):
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case access_program(AbsoluteIndexed):
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++registers.pc.full;
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// Read top half of address.
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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// If this is a read and the top byte doesn't need adjusting, skip that cycle.
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.x;
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if(Storage::operand_ == Storage::address_.halves.high) {
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goto skip_absolute_x_read_bonus_cycle;
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Storage::address_.full += Storage::decoded_.index == Index::X ? registers.x : registers.y;
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if(Storage::decoded_.type == Type::Read && Storage::operand_ == Storage::address_.halves.high) {
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goto access_absolute;
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}
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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skip_absolute_x_read_bonus_cycle:
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(AbsoluteYRead):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.y;
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if(Storage::operand_ == Storage::address_.halves.high) {
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goto skip_absolute_y_read_bonus_cycle;
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}
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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skip_absolute_y_read_bonus_cycle:
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(AbsoluteXWrite):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.x;
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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case access_program(AbsoluteYWrite):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.y;
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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case access_program(AbsoluteXModify):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.x;
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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case access_program(AbsoluteYModify):
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++registers.pc.full;
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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++registers.pc.full;
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Storage::operand_ = Storage::address_.halves.high;
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Storage::address_.full += registers.y;
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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|
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goto fetch_decode;
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// MARK: - Stack.
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case access_program(Pull):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(Push):
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Stack(registers.dec_s()), Storage::operand_);
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goto fetch_decode;
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goto access_absolute;
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// MARK: - Indexed indirect.
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case access_program(IndexedIndirectRead):
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case access_program(IndexedIndirect):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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||||
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case access_program(IndexedIndirectWrite):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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check_interrupt();
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||||
perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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||||
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case access_program(IndexedIndirectModify):
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++registers.pc.full;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::operand_ += registers.x;
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||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
|
||||
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
|
||||
check_interrupt();
|
||||
perform_operation();
|
||||
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
|
||||
goto fetch_decode;
|
||||
goto access_absolute;
|
||||
|
||||
// MARK: - Indirect indexed.
|
||||
case access_program(IndirectIndexedRead):
|
||||
case access_program(IndirectIndexed):
|
||||
++registers.pc.full;
|
||||
|
||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
|
||||
@@ -544,61 +318,14 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
|
||||
Storage::operand_ = Storage::address_.halves.high;
|
||||
Storage::address_.full += registers.y;
|
||||
if(Storage::address_.halves.high == Storage::operand_) {
|
||||
goto skip_indirect_indexed_read_bonus_cycle;
|
||||
if(Storage::decoded_.type == Type::Read && Storage::address_.halves.high == Storage::operand_) {
|
||||
goto access_absolute;
|
||||
}
|
||||
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
|
||||
skip_indirect_indexed_read_bonus_cycle:
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
|
||||
perform_operation();
|
||||
goto fetch_decode;
|
||||
|
||||
|
||||
case access_program(IndirectIndexedWrite):
|
||||
++registers.pc.full;
|
||||
|
||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
|
||||
++Storage::operand_;
|
||||
|
||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
|
||||
|
||||
Storage::operand_ = Storage::address_.halves.high;
|
||||
Storage::address_.full += registers.y;
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
|
||||
check_interrupt();
|
||||
perform_operation();
|
||||
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
|
||||
goto fetch_decode;
|
||||
|
||||
case access_program(IndirectIndexedModify):
|
||||
++registers.pc.full;
|
||||
|
||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
|
||||
++Storage::operand_;
|
||||
|
||||
access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
|
||||
|
||||
Storage::operand_ = Storage::address_.halves.high;
|
||||
Storage::address_.full += registers.y;
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
|
||||
std::swap(Storage::address_.halves.high, Storage::operand_);
|
||||
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
|
||||
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
|
||||
|
||||
check_interrupt();
|
||||
perform_operation();
|
||||
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
|
||||
goto fetch_decode;
|
||||
goto access_absolute;
|
||||
|
||||
// MARK: - Potentially-faulty addressing of SHA/SHX/SHY/SHS.
|
||||
|
||||
|
||||
Reference in New Issue
Block a user