6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-04-21 18:37:11 +00:00
Code Issues Projects Releases Wiki Activity

Change LDR writeback to destination.

Browse Source
This commit is contained in:
Thomas Harte 2024-03-10 22:29:19 -04:00
parent 21278d028c
commit e9e1db7a05
1 changed files with 7 additions and 4 deletions

11
InstructionSets/ARM/Executor.hpp

@ -337,10 +337,13 @@ struct Executor {
// If either postindexing or else with writeback, update base.
if constexpr (!flags.pre_index() || flags.write_back_address()) {
if(transfer.base() == 15) {
registers_.set_pc(offsetted_address);
} else {
registers_[transfer.base()] = offsetted_address;
// Empirically: I think writeback occurs before the access, so shouldn't overwrite on a load.
if(flags.operation() == SingleDataTransferFlags::Operation::STR || transfer.base() != transfer.destination()) {
if(transfer.base() == 15) {
registers_.set_pc(offsetted_address);
} else {
registers_[transfer.base()] = offsetted_address;
}
}
}
}