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Exposes IR during 'internal' operations.
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@ -62,7 +62,7 @@ ProcessorStorage::ProcessorStorage() {
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
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#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
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#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
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#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), nullptr, nullptr, false}}
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#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), &ir_.full, nullptr, false}}
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/// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
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/// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
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#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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