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https://github.com/TomHarte/CLK.git
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Start reforming; data size plus register aren't independent in finding a source.
This commit is contained in:
Thomas Harte
parent
15acb1fc7c
commit
eb100e3b29
@ -182,65 +182,87 @@ void add(IntT &destination, IntT source, Status &status) {
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template <
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Model model,
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Operation operation,
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DataSize data_size,
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typename FlowControllerT
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typename InstructionT,
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typename FlowControllerT,
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typename RegistersT,
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typename MemoryT,
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typename IOT
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> void perform(
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CPU::RegisterPair16 &destination,
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CPU::RegisterPair16 &source,
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const InstructionT &instruction,
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Status &status,
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FlowControllerT &flow_controller
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[[maybe_unused]] FlowControllerT &flow_controller,
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RegistersT ®isters,
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[[maybe_unused]] MemoryT &memory,
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[[maybe_unused]] IOT &io
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) {
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switch(operation) {
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case Operation::AAA: Primitive::aaa(destination, status); break;
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case Operation::AAD: Primitive::aad(destination, source.halves.low, status); break;
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case Operation::AAM: Primitive::aam(destination, source.halves.low, status); break;
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case Operation::AAS: Primitive::aas(destination, status); break;
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using IntT = typename DataSizeType<data_size>::type;
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case Operation::ADC:
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static_assert(operation != Operation::ADC || data_size == DataSize::Byte || data_size == DataSize::Word);
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switch(data_size) {
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case DataSize::Byte: Primitive::adc(destination.halves.low, source.halves.low, status); break;
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case DataSize::Word: Primitive::adc(destination.full, source.full, status); break;
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}
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break;
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case Operation::ADD:
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static_assert(operation != Operation::ADD || data_size == DataSize::Byte || data_size == DataSize::Word);
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switch(data_size) {
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case DataSize::Byte: Primitive::add(destination.halves.low, source.halves.low, status); break;
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case DataSize::Word: Primitive::add(destination.full, source.full, status); break;
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}
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break;
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// Establish source() and destination() shorthand to fetch data if necessary.
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IntT fetched_data;
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bool needs_writeback = false;
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auto data = [&](DataPointer source) -> IntT& {
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// TODO.
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return fetched_data;
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};
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auto source = [&]() -> IntT& { return data(instruction.source()); };
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auto destination = [&]() -> IntT& { return data(instruction.destination()); };
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// Guide to the below:
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//
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// * use hard-coded register names where appropriate;
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// * return directly if there is definitely no possible write back to RAM;
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// * otherwise use the source() and destination() lambdas, and break in order to allow a writeback if necessary.
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switch(instruction.operation) {
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case Operation::AAA: Primitive::aaa(registers.ax(), status); return;
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case Operation::AAD: Primitive::aad(registers.ax(), instruction.immediate(), status); return;
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case Operation::AAM: Primitive::aam(registers.ax(), instruction.immediate(), status); return;
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case Operation::AAS: Primitive::aas(registers.ax(), status); return;
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case Operation::ADC: Primitive::adc(destination(), source(), status); break;
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case Operation::ADD: Primitive::add(destination(), source(), status); break;
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}
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(void)flow_controller;
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// Write to memory if required to complete this operation.
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if(needs_writeback) {
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// TODO.
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}
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}
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/*template <
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template <
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Model model,
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typename InstructionT,
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typename FlowControllerT,
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typename DataPointerResolverT,
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typename RegistersT,
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typename MemoryT,
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typename IOT,
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Operation operation
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typename IOT
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> void perform(
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const InstructionT &instruction,
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Status &status,
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FlowControllerT &flow_controller,
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DataPointerResolverT &resolver,
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RegistersT ®isters,
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MemoryT &memory,
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IOT &io
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) {
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switch((operation != Operation::Invalid) ? operation : instruction.operation) {
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default:
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assert(false);
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return;
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// Dispatch to a function just like this that is specialised on data size.
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// Fetching will occur in that specialised function, per the overlapping
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// meaning of register names.
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switch(instruction.operation_size()) {
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case DataSize::Byte:
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perform<model, DataSize::Byte>(instruction, status, flow_controller, registers, memory, io);
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break;
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case DataSize::Word:
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perform<model, DataSize::Word>(instruction, status, flow_controller, registers, memory, io);
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break;
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case DataSize::DWord:
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perform<model, DataSize::DWord>(instruction, status, flow_controller, registers, memory, io);
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break;
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case DataSize::None:
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perform<model, DataSize::None>(instruction, status, flow_controller, registers, memory, io);
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break;
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}
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}*/
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}
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}
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@ -370,6 +370,10 @@ enum class DataSize: uint8_t {
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None = 3,
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};
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template <DataSize size> struct DataSizeType { using type = uint8_t; };
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template <> struct DataSizeType<DataSize::Word> { using type = uint16_t; };
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template <> struct DataSizeType<DataSize::DWord> { using type = uint32_t; };
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constexpr int byte_size(DataSize size) {
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return (1 << int(size)) & 7;
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}
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@ -16,33 +16,27 @@
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namespace InstructionSet::x86 {
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/// Performs @c instruction using @c resolver to obtain to query @c registers and/or @c memory as required, using @c io for port input/output,
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/// Performs @c instruction querying @c registers and/or @c memory as required, using @c io for port input/output,
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/// and providing any flow control effects to @c flow_controller.
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///
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/// Any change in processor status will be applied to @c status.
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///
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/// If the template parameter @c operation is not @c Operation::Undefined then that operation will be performed, ignoring
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/// whatever is specifed in @c instruction.
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template <
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Model model,
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typename InstructionT,
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typename FlowControllerT,
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typename DataPointerResolverT,
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typename RegistersT,
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typename MemoryT,
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typename IOT,
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Operation operation = Operation::Invalid
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typename IOT
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> void perform(
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const InstructionT &instruction,
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Status &status,
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FlowControllerT &flow_controller,
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DataPointerResolverT &resolver,
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RegistersT ®isters,
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MemoryT &memory,
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IOT &io
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);
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template <
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/*template <
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Model model,
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Operation operation,
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DataSize data_size,
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@ -64,7 +58,7 @@ template <
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CPU::RegisterPair16 &source,
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Status &status,
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FlowControllerT &flow_controller
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);
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);*/
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}
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@ -187,25 +187,25 @@ constexpr char TestSuiteHome[] = "/Users/tharte/Projects/ProcessorTests/8088/v1"
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}
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- (void)testExecution {
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CPU::RegisterPair16 source, dest;
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InstructionSet::x86::Status status;
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struct NoFlow {
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} flow_controller;
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dest.full = 0xff;
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source.full = 10;
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InstructionSet::x86::perform<
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InstructionSet::x86::Model::i8086,
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InstructionSet::x86::Operation::ADD,
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InstructionSet::x86::DataSize::Byte
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>(
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dest,
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source,
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status,
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flow_controller
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);
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// CPU::RegisterPair16 source, dest;
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// InstructionSet::x86::Status status;
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// struct NoFlow {
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// } flow_controller;
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//
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// dest.full = 0xff;
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// source.full = 10;
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//
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// InstructionSet::x86::perform<
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// InstructionSet::x86::Model::i8086,
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// InstructionSet::x86::Operation::ADD,
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// InstructionSet::x86::DataSize::Byte
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// >(
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// dest,
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// source,
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// status,
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// flow_controller
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// );
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//
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}
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@end
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