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https://github.com/TomHarte/CLK.git
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Fix $8e data size, add $8c.
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1afcbba218
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@ -233,9 +233,12 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
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case 0x89: MemRegReg(MOV, MemReg_Reg, data_size_); break;
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case 0x8a: MemRegReg(MOV, Reg_MemReg, DataSize::Byte); break;
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case 0x8b: MemRegReg(MOV, Reg_MemReg, data_size_); break;
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// 0x8c: not used.
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case 0x8c:
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RequiresMin(i80286); // TODO: or is this 80386?
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MemRegReg(MOV, MemReg_Seg, DataSize::Word);
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break;
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case 0x8d: MemRegReg(LEA, Reg_MemReg, data_size_); break;
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case 0x8e: MemRegReg(MOV, SegReg, data_size_); break;
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case 0x8e: MemRegReg(MOV, Seg_MemReg, DataSize::Word); break;
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case 0x8f: MemRegReg(POP, MemRegPOP, data_size_); break;
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case 0x90: Complete(NOP, None, None, DataSize::None); break; // Or XCHG AX, AX?
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@ -430,10 +433,15 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
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++consumed_;
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Source memreg;
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// TODO: can I just eliminate these lookup tables given the deliberate ordering within Source?
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constexpr Source reg_table[8] = {
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Source::eAX, Source::eCX, Source::eDX, Source::eBX,
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Source::eSPorAH, Source::eBPorCH, Source::eSIorDH, Source::eDIorBH,
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};
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constexpr Source seg_table[6] = {
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Source::ES, Source::CS, Source::SS, Source::DS, Source::FS, Source::GS
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};
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switch(mod) {
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default: {
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const DataSize sizes[] = {DataSize::Byte, data_size_};
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@ -495,20 +503,29 @@ std::pair<int, typename Decoder<model>::InstructionT> Decoder<model>::decode(con
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}
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break;
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case ModRegRMFormat::SegReg: {
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source_ = memreg;
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constexpr Source seg_table[4] = {
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Source::ES, Source::CS,
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Source::SS, Source::DS,
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};
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if(reg & 4) {
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case ModRegRMFormat::Seg_MemReg:
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case ModRegRMFormat::MemReg_Seg:
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// The 16-bit chips have four segment registers;
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// the 80386 onwards has six.
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if(!is_32bit(model) && reg > 3) {
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undefined();
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} else if(reg > 5) {
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undefined();
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}
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destination_ = seg_table[reg];
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} break;
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if(modregrm_format_ == ModRegRMFormat::Seg_MemReg) {
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source_ = memreg;
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destination_ = seg_table[reg];
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// 80286 and later disallow MOV to CS.
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if(model >= Model::i80286 && destination_ == Source::CS) {
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undefined();
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}
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} else {
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source_ = seg_table[reg];
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destination_ = memreg;
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}
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break;
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case ModRegRMFormat::MemRegROL_to_SAR:
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destination_ = memreg;
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@ -65,7 +65,7 @@ template <Model model> class Decoder {
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/// are packaged into an Instruction.
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enum class ModRegRMFormat: uint8_t {
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// Parse the ModRegRM for mode, register and register/memory fields
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// and populate the source_ and destination_ fields appropriate.
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// and populate the source_ and destination_ fields appropriately.
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MemReg_Reg,
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Reg_MemReg,
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@ -82,7 +82,8 @@ template <Model model> class Decoder {
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// Parse for mode and register/memory fields, populating the
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// source_ field with the result. Fills destination_ with a segment
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// register based on the reg field.
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SegReg,
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Seg_MemReg,
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MemReg_Seg,
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//
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// 'Group 1'
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