6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-21 21:33:54 +00:00
Code Issues Projects Releases Wiki Activity

Add RAM paging.

Browse Source
This commit is contained in:
Thomas Harte 2023-01-16 11:52:08 -05:00
parent 1769c24531
commit eb51ff5cdf
1 changed files with 18 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Machines/MSX/MSX.cpp
View File

@ -628,11 +628,24 @@ class ConcreteMachine:
clock_.write(next_clock_register_, *cycle.value);
break;
case 0xfc: case 0xfd: case 0xfe: case 0xff:
// 1. Propagate to all handlers.
// 2. Apply to RAM.
printf("RAM banking %02x: %02x\n", port, *cycle.value);
break;
case 0xfc: case 0xfd: case 0xfe: case 0xff: {
if constexpr (model == Target::Model::MSX1) {
break;
}
// TODO: Propagate to all handlers.
// Apply to RAM.
const uint16_t region = uint16_t((port - 0xfc) << 14);
const size_t base = size_t(*cycle.value) << 14;
if(base < RAMSize) {
ram_slot().template map<MemorySlot::AccessType::ReadWrite>(base, region, 0x4000);
} else {
ram_slot().unmap(region, 0x4000);
}
update_paging();
} break;
default:
printf("Unhandled write %02x of %02x\n", address & 0xff, *cycle.value);