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Adjusts JSR behaviour and further extends MOVE.

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This commit is contained in:
Thomas Harte 2019-04-15 22:02:52 -04:00
parent 5330267d16
commit ebcae25762
3 changed files with 33 additions and 9 deletions
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2
Processors/68000/Implementation/68000Implementation.hpp
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@ -946,8 +946,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
case int(MicroOp::Action::PrepareJSR): case int(MicroOp::Action::PrepareJSR):
destination_bus_data_[0] = program_counter_; destination_bus_data_[0] = program_counter_;
effective_address_[1].full = address_[7].full - 2;
address_[7].full -= 4; address_[7].full -= 4;
effective_address_[1].full = address_[7].full;
break; break;
case int(MicroOp::Action::PrepareRTS): case int(MicroOp::Action::PrepareRTS):

38
Processors/68000/Implementation/68000Storage.cpp
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@ -1529,20 +1529,20 @@ struct ProcessorStorageConstructor {
case Ind: // JSR (An) case Ind: // JSR (An)
storage_.instructions[instruction].source = &storage_.address_[ea_register]; storage_.instructions[instruction].source = &storage_.address_[ea_register];
op(Action::PrepareJSR); op(Action::PrepareJSR);
op(Action::PerformOperation, seq("np nS ns np")); op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
break; break;
case d16PC: // JSR (d16, PC) case d16PC: // JSR (d16, PC)
case d16An: // JSR (d16, An) case d16An: // JSR (d16, An)
op(Action::PrepareJSR); op(Action::PrepareJSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np nS ns np")); op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np nW+ nw np", { ea(1), ea(1) }));
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
case d8PCXn: // JSR (d8, PC, Xn) case d8PCXn: // JSR (d8, PC, Xn)
case d8AnXn: // JSR (d8, An, Xn) case d8AnXn: // JSR (d8, An, Xn)
op(Action::PrepareJSR); op(Action::PrepareJSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n nn np nS ns np")); op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
op(Action::PerformOperation); op(Action::PerformOperation);
break; break;
@ -1550,13 +1550,13 @@ struct ProcessorStorageConstructor {
op(Action::None, seq("np")); op(Action::None, seq("np"));
op(Action::PrepareJSR); op(Action::PrepareJSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask); op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nS ns np")); op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break; break;
case XXXw: // JSR (xxx).W case XXXw: // JSR (xxx).W
op(Action::PrepareJSR); op(Action::PrepareJSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask); op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nS ns np")); op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break; break;
} }
} break; } break;
@ -2059,7 +2059,15 @@ struct ProcessorStorageConstructor {
case bw2(Dn, d16PC): // MOVE.bw Dn, (d16, PC) case bw2(Dn, d16PC): // MOVE.bw Dn, (d16, PC)
case bw2(Dn, d8PCXn): // MOVE.bw Dn, (d8, PC, Xn) case bw2(Dn, d8PCXn): // MOVE.bw Dn, (d8, PC, Xn)
op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq(pseq("np", destination_mode))); op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq(pseq("np", destination_mode)));
op(Action::PerformOperation, seq("nw np", { ea(1) })); op(Action::PerformOperation, seq("nw np", { ea(1) }, !is_byte_access));
break;
case l2(Dn, d16An): // MOVE.l Dn, (d16, An)
case l2(Dn, d8AnXn): // MOVE.l Dn, (d8, An, Xn)
case l2(Dn, d16PC): // MOVE.l Dn, (d16, PC)
case l2(Dn, d8PCXn): // MOVE.l Dn, (d8, PC, Xn)
op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq(pseq("np", destination_mode)));
op(Action::PerformOperation, seq("nW+ nw np", { ea(1), ea(1) }));
break; break;
case bw2(Ind, d16An): // MOVE.bw (An), (d16, An) case bw2(Ind, d16An): // MOVE.bw (An), (d16, An)
@ -2070,13 +2078,29 @@ struct ProcessorStorageConstructor {
case bw2(PostInc, d16PC): // MOVE.bw (An)+, (d16, PC) case bw2(PostInc, d16PC): // MOVE.bw (An)+, (d16, PC)
case bw2(Ind, d8PCXn): // MOVE.bw (An), (d8, PC, Xn) case bw2(Ind, d8PCXn): // MOVE.bw (An), (d8, PC, Xn)
case bw2(PostInc, d8PCXn): // MOVE.bw (An)+, (d8, PC, Xn) case bw2(PostInc, d8PCXn): // MOVE.bw (An)+, (d8, PC, Xn)
op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq("nr", { &storage_.address_[ea_register].full }, !is_byte_access)); op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq("nr", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq(pseq("np nw np", destination_mode), { ea(1) }, !is_byte_access)); op(Action::PerformOperation, seq(pseq("np nw np", destination_mode), { ea(1) }, !is_byte_access));
if(ea_mode == PostInc) { if(ea_mode == PostInc) {
op(increment_action | MicroOp::SourceMask); op(increment_action | MicroOp::SourceMask);
} }
break; break;
case l2(Ind, d16An): // MOVE.l (An), (d16, An)
case l2(PostInc, d16An): // MOVE.l (An)+, (d16, An)
case l2(Ind, d8AnXn): // MOVE.l (An), (d8, An, Xn)
case l2(PostInc, d8AnXn): // MOVE.l (An)+, (d8, An, Xn)
case l2(Ind, d16PC): // MOVE.l (An), (d16, PC)
case l2(PostInc, d16PC): // MOVE.l (An)+, (d16, PC)
case l2(Ind, d8PCXn): // MOVE.l (An), (d8, PC, Xn)
case l2(PostInc, d8PCXn): // MOVE.l (An)+, (d8, PC, Xn)
op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask);
op(calc_action_for_mode(destination_mode) | MicroOp::DestinationMask, seq("nR+ nr", { ea(0), ea(0) }));
op(Action::PerformOperation, seq(pseq("np nW+ nw np", destination_mode), { ea(1), ea(1) }));
if(ea_mode == PostInc) {
op(increment_action | MicroOp::SourceMask);
}
break;
// case 0x0405: // MOVE -(An), (d16, An) // case 0x0405: // MOVE -(An), (d16, An)
// n nr np nw // n nr np nw
// continue; // continue;

2
Processors/68000/Implementation/68000Storage.hpp
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@ -223,7 +223,7 @@ class ProcessorStorage {
MOVEMtoMComplete, MOVEMtoMComplete,
// (i) copies the current program counter to destination_bus_data_; // (i) copies the current program counter to destination_bus_data_;
// (ii) copies the stack pointer minus 2 to effective_address_[1]; // (ii) copies the stack pointer minus 4 to effective_address_[1];
// (iii) decrements the stack pointer by four. // (iii) decrements the stack pointer by four.
PrepareJSR, PrepareJSR,