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Conquers another page of instructions; adds supervisor flag.
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Thomas Harte
parent
db50b0fe23
commit
ebfa35c2c7
@ -27,10 +27,15 @@ Instruction Decoder::decode(uint32_t opcode) {
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// I've decided to hew directly to the mnemonics.
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#define Bind(mask, operation) case mask: return Instruction(Operation::operation, opcode);
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#define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true);
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#define BindConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode); \
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return Instruction(opcode);
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#define BindSupervisorConditional(condition, mask, operation) \
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case mask: \
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if(condition()) return Instruction(Operation::operation, opcode, true); \
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return Instruction(opcode);
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#define Six(x) (unsigned(x) << 26)
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#define SixTen(x, y) (Six(x) | (y << 1))
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@ -81,6 +86,19 @@ Instruction Decoder::decode(uint32_t opcode) {
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BindConditional(is64bit, SixTen(0b011111, 0b0000001001), mulhdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000010101), ldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000011011), sldx);
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BindConditional(is64bit, SixTen(0b011111, 0b0000110101), ldux);
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BindConditional(is64bit, SixTen(0b011111, 0b0000111010), cntlzdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001000100), td);
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BindConditional(is64bit, SixTen(0b011111, 0b0001001001), mulhdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0001010100), ldarx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010010101), stdx);
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BindConditional(is64bit, SixTen(0b011111, 0b0010110101), stdux);
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BindConditional(is64bit, SixTen(0b011111, 0b0011101001), mulld); BindConditional(is64bit, SixTen(0b011111, 0b1011101001), mulld);
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BindConditional(is64bit, SixTen(0b011111, 0b0101010101), lwax);
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BindConditional(is64bit, SixTen(0b011111, 0b0101110101), lwaux);
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// BindConditional(is64bit, SixTen(0b011111, 0b1100111011), sradix); // TODO: encoding is unclear re: the sh flag.
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BindConditional(is64bit, SixTen(0b011111, 0b0110110010), slbie);
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BindConditional(is64bit, SixTen(0b011111, 0b0111001001), divdux); BindConditional(is64bit, SixTen(0b011111, 0b1111001001), divdux);
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Bind(SixTen(0b010011, 0b0000000000), mcrf);
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Bind(SixTen(0b010011, 0b0000010000), bclrx);
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@ -108,14 +126,67 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(SixTen(0b011111, 0b0000011100), andx);
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Bind(SixTen(0b011111, 0b0000100000), cmpl);
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Bind(SixTen(0b011111, 0b0000101000), subfx); Bind(SixTen(0b011111, 0b1000101000), subfx);
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Bind(SixTen(0b011111, 0b0000110110), dcbst);
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Bind(SixTen(0b011111, 0b0000110111), lwzux);
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Bind(SixTen(0b011111, 0b0000111100), andcx);
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Bind(SixTen(0b011111, 0b0001001011), mulhwx);
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Bind(SixTen(0b011111, 0b0001010011), mfmsr);
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Bind(SixTen(0b011111, 0b0001010110), dcbf);
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Bind(SixTen(0b011111, 0b0001010111), lbzx);
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Bind(SixTen(0b011111, 0b0001101000), negx); Bind(SixTen(0b011111, 0b1001101000), negx);
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Bind(SixTen(0b011111, 0b0001110111), lbzux);
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Bind(SixTen(0b011111, 0b0001111100), norx);
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Bind(SixTen(0b011111, 0b0010001000), subfex); Bind(SixTen(0b011111, 0b1010001000), subfex);
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Bind(SixTen(0b011111, 0b0010001010), addex); Bind(SixTen(0b011111, 0b1010001010), addex);
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Bind(SixTen(0b011111, 0b0010010000), mtcrf);
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Bind(SixTen(0b011111, 0b0010010010), mtmsr);
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Bind(SixTen(0b011111, 0b0010010111), stwx);
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Bind(SixTen(0b011111, 0b0010110111), stwux);
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Bind(SixTen(0b011111, 0b0011001000), subfzex); Bind(SixTen(0b011111, 0b1011001000), subfzex);
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Bind(SixTen(0b011111, 0b0011001010), addzex); Bind(SixTen(0b011111, 0b1011001010), addzex);
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Bind(SixTen(0b011111, 0b0011010111), stbx);
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Bind(SixTen(0b011111, 0b0011101000), subfmex); Bind(SixTen(0b011111, 0b1011101000), subfmex);
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Bind(SixTen(0b011111, 0b0011101010), addmex); Bind(SixTen(0b011111, 0b1011101010), addmex);
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Bind(SixTen(0b011111, 0b0011101011), mullwx); Bind(SixTen(0b011111, 0b1011101011), mullwx);
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Bind(SixTen(0b011111, 0b0011110110), dcbtst);
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Bind(SixTen(0b011111, 0b0011110111), stbux);
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Bind(SixTen(0b011111, 0b0100001010), addx); Bind(SixTen(0b011111, 0b1100001010), addx);
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Bind(SixTen(0b011111, 0b0100010110), dcbt);
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Bind(SixTen(0b011111, 0b0100010111), lhzx);
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Bind(SixTen(0b011111, 0b0100011100), eqvx);
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Bind(SixTen(0b011111, 0b0100110110), eciwx);
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Bind(SixTen(0b011111, 0b0100110111), lhzux);
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Bind(SixTen(0b011111, 0b0100111100), xorx);
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Bind(SixTen(0b011111, 0b0101010111), lhax);
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Bind(SixTen(0b011111, 0b0101110011), mftb);
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Bind(SixTen(0b011111, 0b0101110111), lhaux);
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Bind(SixTen(0b011111, 0b0110010111), sthx);
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Bind(SixTen(0b011111, 0b0110011100), orcx);
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Bind(SixTen(0b011111, 0b0110110110), ecowx);
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Bind(SixTen(0b011111, 0b0110110111), sthux);
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Bind(SixTen(0b011111, 0b0110111100), orx);
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Bind(SixTen(0b011111, 0b0111001011), divwux); Bind(SixTen(0b011111, 0b1111001011), divwux);
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Bind(SixTen(0b011111, 0b0111010110), dcbi);
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Bind(SixTen(0b011111, 0b0101010011), mfspr); // Flagged as "supervisor and user"?
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Bind(SixTen(0b011111, 0b0111010011), mtspr); // Flagged as "supervisor and user"?
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BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011010010), mtsr);
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BindSupervisorConditional(is32bit, SixTen(0b011111, 0b0011110010), mtsrin);
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BindSupervisor(SixTen(0b011111, 0b0100110010), tlbie); // TODO: mark formally as optional?
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BindSupervisor(SixTen(0b011111, 0b0101110010), tlbia); // TODO: mark formally as optional?
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}
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// TODO: stwcx., stdcx.
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// Check for sc.
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if((opcode & 0b010001'00000'00000'00000000000000'1'0) == 0b010001'00000'00000'00000000000000'1'0) {
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return Instruction(Operation::sc, opcode);
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}
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#undef Six
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#undef SixTen
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#undef Bind
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#undef BindConditional
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@ -46,17 +46,20 @@ enum class Operation: uint8_t {
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sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu,
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stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx,
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stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx,
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subfex, subfic, subfmex, subfzex, sync, tlbie, tw, twi, xorx, xori, xoris,
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subfex, subfic, subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb,
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// 32-bit, supervisor level.
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dcbi,
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// Supervisor, optional.
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tlbia, tlbie,
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// Optional.
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fresx, frsqrtex, fselx, fsqrtx, frsqrtsx, slbia, slbie,
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// 64-bit only PowerPC instructions.
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cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx, tdi, mulhdux, ldx,
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sldx
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sldx, ldux, td, mulhdx, ldarx, stdx, stdux, mulld, lwax, lwaux, sradix,
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};
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/*!
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@ -67,10 +70,11 @@ enum class Operation: uint8_t {
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*/
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struct Instruction {
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const Operation operation = Operation::Undefined;
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const bool is_supervisor = false;
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const uint32_t opcode = 0;
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Instruction(uint32_t opcode) : opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode) : operation(operation), opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
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// Instruction fields are decoded below; naming is as directly dictated by
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// Motorola's documentation, and the definitions below are sorted by synonym.
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@ -100,6 +104,7 @@ struct Instruction {
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int l() { return (opcode >> 21) & 0x01; }
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int aa() { return (opcode >> 1) & 0x01; }
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int lk() { return opcode & 0x01; }
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int rc() { return opcode & 0x01; }
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};
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struct Decoder {
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@ -115,6 +120,10 @@ struct Decoder {
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return false;
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}
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bool is32bit() {
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return true;
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}
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bool is601() {
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return model_ == Model::MPC601;
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}
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