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https://github.com/TomHarte/CLK.git
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Added a potential branch for the newer TOS memory map.
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@ -10,6 +10,7 @@
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#include "../CRTMachine.hpp"
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//#define LOG_TRACE
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/AY38910/AY38910.hpp"
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@ -250,12 +251,16 @@ class ConcreteMachine:
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memory_map_[0] = BusDevice::MostlyRAM;
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int c = 1;
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for(; c < 0x08; ++c) memory_map_[c] = BusDevice::RAM;
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for(; c < 0xff; ++c) memory_map_[c] = BusDevice::Unassigned;
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const bool is_early_tos = true;
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if(is_early_tos) {
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for(c = 0xfc; c < 0xff; ++c) memory_map_[c] = BusDevice::ROM;
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} else {
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for(c = 0xe0; c < 0xe4; ++c) memory_map_[c] = BusDevice::ROM;
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}
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// This is appropriate for: TOS 1.x, no cartridge.
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for(; c < 0xfc; ++c) memory_map_[c] = BusDevice::Unassigned;
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for(; c < 0xff; ++c) memory_map_[c] = BusDevice::ROM;
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memory_map_[0xfa] = memory_map_[0xfb] = BusDevice::Cartridge;
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memory_map_[0xff] = BusDevice::IO;
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midi_acia_->set_interrupt_delegate(this);
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@ -356,7 +361,7 @@ class ConcreteMachine:
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case BusDevice::IO:
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switch(address) {
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default:
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assert(false);
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// assert(false);
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case 0x7fc000:
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/* Memory controller configuration:
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@ -70,7 +70,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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const HalfCycles remaining_duration = duration + half_cycles_left_to_run_;
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#ifdef LOG_TRACE
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static bool should_log = false;
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static bool should_log = true;
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#endif
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// This loop counts upwards rather than downwards because it simplifies calculation of
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@ -310,7 +310,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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const uint32_t fetched_pc = (program_counter_.full - 4)&0xffffff;
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// should_log |= fetched_pc == 0x6d9c;
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should_log = (fetched_pc >= 0x41806A && fetched_pc <= 0x418618);
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// should_log = (fetched_pc >= 0x41806A && fetched_pc <= 0x418618);
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// should_log |= fetched_pc == 0x4012A2;
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// should_log &= fetched_pc != 0x4012AE;
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