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Merge pull request #219 from TomHarte/ConstSafety
Makes all of PartialMachineCycle const
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commit
ecd3350a6f
@ -92,11 +92,12 @@ struct PartialMachineCycle {
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InputStart,
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OutputStart,
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InterruptStart,
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} operation;
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HalfCycles length;
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uint16_t *address;
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uint8_t *value;
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bool was_requested;
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};
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const Operation operation;
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const HalfCycles length;
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const uint16_t *const address;
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uint8_t *const value;
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const bool was_requested;
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inline bool expects_action() const {
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return operation <= Operation::Interrupt;
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@ -107,6 +108,17 @@ struct PartialMachineCycle {
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inline bool is_wait() const {
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return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait;
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}
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PartialMachineCycle(const PartialMachineCycle &rhs) noexcept :
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operation(rhs.operation),
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length(rhs.length),
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address(rhs.address),
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value(rhs.value),
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was_requested(rhs.was_requested) {}
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PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept :
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operation(operation), length(length), address(address), value(value), was_requested(was_requested) {}
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PartialMachineCycle() noexcept :
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operation(Internal), length(0), address(nullptr), value(nullptr), was_requested(false) {}
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};
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class BusHandler {
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@ -118,31 +130,31 @@ class BusHandler {
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};
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// Elemental bus operations
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#define ReadOpcodeStart() {PartialMachineCycle::ReadOpcodeStart, HalfCycles(3), &pc_.full, &operation_, false}
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#define ReadOpcodeWait(f) {PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f}
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#define ReadOpcodeEnd() {PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false}
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#define ReadOpcodeStart() PartialMachineCycle(PartialMachineCycle::ReadOpcodeStart, HalfCycles(3), &pc_.full, &operation_, false)
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#define ReadOpcodeWait(f) PartialMachineCycle(PartialMachineCycle::ReadOpcodeWait, HalfCycles(2), &pc_.full, &operation_, f)
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#define ReadOpcodeEnd() PartialMachineCycle(PartialMachineCycle::ReadOpcode, HalfCycles(1), &pc_.full, &operation_, false)
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#define Refresh(len) {PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false}
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#define Refresh(len) PartialMachineCycle(PartialMachineCycle::Refresh, HalfCycles(len), &refresh_addr_.full, nullptr, false)
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#define ReadStart(addr, val) {PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false}
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#define ReadWait(l, addr, val, f) {PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f}
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#define ReadEnd(addr, val) {PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false}
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#define ReadStart(addr, val) PartialMachineCycle(PartialMachineCycle::ReadStart, HalfCycles(3), &addr.full, &val, false)
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#define ReadWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::ReadWait, HalfCycles(l), &addr.full, &val, f)
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#define ReadEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Read, HalfCycles(3), &addr.full, &val, false)
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#define WriteStart(addr, val) {PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false}
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#define WriteWait(l, addr, val, f) {PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f}
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#define WriteEnd(addr, val) {PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false}
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#define WriteStart(addr, val) PartialMachineCycle(PartialMachineCycle::WriteStart,HalfCycles(3), &addr.full, &val, false)
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#define WriteWait(l, addr, val, f) PartialMachineCycle(PartialMachineCycle::WriteWait, HalfCycles(l), &addr.full, &val, f)
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#define WriteEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Write, HalfCycles(3), &addr.full, &val, false)
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#define InputStart(addr, val) {PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false}
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#define InputWait(addr, val, f) {PartialMachineCycle::InputWait, HalfCycles(2), &addr.full, &val, f}
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#define InputEnd(addr, val) {PartialMachineCycle::Input, HalfCycles(3), &addr.full, &val, false}
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#define InputStart(addr, val) PartialMachineCycle(PartialMachineCycle::InputStart, HalfCycles(3), &addr.full, &val, false)
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#define InputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::InputWait, HalfCycles(2), &addr.full, &val, f)
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#define InputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Input, HalfCycles(3), &addr.full, &val, false)
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#define OutputStart(addr, val) {PartialMachineCycle::OutputStart, HalfCycles(3), &addr.full, &val, false}
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#define OutputWait(addr, val, f) {PartialMachineCycle::OutputWait, HalfCycles(2), &addr.full, &val, f}
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#define OutputEnd(addr, val) {PartialMachineCycle::Output, HalfCycles(3), &addr.full, &val, false}
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#define OutputStart(addr, val) PartialMachineCycle(PartialMachineCycle::OutputStart, HalfCycles(3), &addr.full, &val, false)
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#define OutputWait(addr, val, f) PartialMachineCycle(PartialMachineCycle::OutputWait, HalfCycles(2), &addr.full, &val, f)
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#define OutputEnd(addr, val) PartialMachineCycle(PartialMachineCycle::Output, HalfCycles(3), &addr.full, &val, false)
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#define IntAckStart(length, val) {PartialMachineCycle::InterruptStart, HalfCycles(length), nullptr, &val, false}
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#define IntWait(val) {PartialMachineCycle::InterruptWait, HalfCycles(2), nullptr, &val, true}
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#define IntAckEnd(val) {PartialMachineCycle::Interrupt, HalfCycles(3), nullptr, &val, false}
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#define IntAckStart(length, val) PartialMachineCycle(PartialMachineCycle::InterruptStart, HalfCycles(length), nullptr, &val, false)
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#define IntWait(val) PartialMachineCycle(PartialMachineCycle::InterruptWait, HalfCycles(2), nullptr, &val, true)
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#define IntAckEnd(val) PartialMachineCycle(PartialMachineCycle::Interrupt, HalfCycles(3), nullptr, &val, false)
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// A wrapper to express a bus operation as a micro-op
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@ -438,13 +450,13 @@ template <class T, bool uses_bus_request> class Processor {
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}
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// Allocate a landing area.
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target.all_operations.resize(number_of_micro_ops);
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std::vector<size_t> operation_indices;
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target.instructions.resize(256, nullptr);
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// Copy in all programs and set pointers.
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// Copy in all programs, recording where they go.
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size_t destination = 0;
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for(size_t c = 0; c < 256; c++) {
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target.instructions[c] = &target.all_operations[destination];
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operation_indices.push_back(target.all_operations.size());
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for(size_t t = 0; t < lengths[c];) {
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// Skip zero-length bus cycles.
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if(table[c][t].type == MicroOp::BusOperation && table[c][t].machine_cycle.length.as_int() == 0) {
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@ -462,11 +474,18 @@ template <class T, bool uses_bus_request> class Processor {
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t++;
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}
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}
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target.all_operations[destination] = table[c][t];
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target.all_operations.emplace_back(table[c][t]);
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destination++;
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t++;
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}
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}
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// Since the vector won't change again, it's now safe to set pointers.
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size_t c = 0;
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for(size_t index : operation_indices) {
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target.instructions[c] = &target.all_operations[index];
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c++;
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}
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}
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void assemble_ed_page(InstructionPage &target) {
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@ -774,10 +793,9 @@ template <class T, bool uses_bus_request> class Processor {
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void copy_program(const MicroOp *source, std::vector<MicroOp> &destination) {
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size_t length = 0;
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while(!isTerminal(source[length].type)) length++;
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destination.resize(length + 1);
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size_t pointer = 0;
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while(true) {
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destination[pointer] = source[pointer];
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destination.emplace_back(source[pointer]);
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if(isTerminal(source[pointer].type)) break;
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pointer++;
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}
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