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Introduce the principle that a Serial::Line can be two-wire — clock + data.

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This commit is contained in:
Thomas Harte
2021-11-06 16:54:20 -07:00
parent c0c2b5e3a9
commit ecfe68d70f
9 changed files with 71 additions and 45 deletions
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Components/6850/6850.cpp
+1 -1
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@@ -148,7 +148,7 @@ uint8_t ACIA::parity(uint8_t value) {
return value ^ (parity_ == Parity::Even);
}
bool ACIA::serial_line_did_produce_bit(Serial::Line *, int bit) {
bool ACIA::serial_line_did_produce_bit(Serial::Line<false> *, int bit) {
// Shift this bit into the 11-bit input register; this is big enough to hold
// the largest transmission symbol.
++bits_received_;