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Add RaiseException macro.

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This commit is contained in:
Thomas Harte 2022-05-25 15:45:09 -04:00
parent f2a7660390
commit ee58301a46
1 changed files with 12 additions and 10 deletions
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22
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -317,6 +317,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
prefetch_.high = prefetch_.low; \ prefetch_.high = prefetch_.low; \
ReadProgramWord(prefetch_.low) ReadProgramWord(prefetch_.low)
// Raises the exception with integer vector x — x is the vector identifier,
// not its address.
#define RaiseException(x) \
exception_vector_ = x; \
MoveToStateSpecific(StandardException);
using Mode = InstructionSet::M68k::AddressingMode; using Mode = InstructionSet::M68k::AddressingMode;
// Otherwise continue for all time, until back in debt. // Otherwise continue for all time, until back in debt.
@ -577,8 +583,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// Potentially perform a trace. // Potentially perform a trace.
if(should_trace_) { if(should_trace_) {
exception_vector_ = InstructionSet::M68k::Exception::Trace; RaiseException(InstructionSet::M68k::Exception::Trace);
MoveToStateSpecific(StandardException);
} }
// Capture the current trace flag. // Capture the current trace flag.
@ -1745,14 +1750,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CHK_was_over): BeginState(CHK_was_over):
IdleBus(2); // nn IdleBus(2); // nn
instruction_address_.l = program_counter_.l - 4; instruction_address_.l = program_counter_.l - 4;
exception_vector_ = InstructionSet::M68k::Exception::CHK; RaiseException(InstructionSet::M68k::Exception::CHK);
MoveToStateSpecific(StandardException);
BeginState(CHK_was_under): BeginState(CHK_was_under):
IdleBus(3); // n nn IdleBus(3); // n nn
instruction_address_.l = program_counter_.l - 4; instruction_address_.l = program_counter_.l - 4;
exception_vector_ = InstructionSet::M68k::Exception::CHK; RaiseException(InstructionSet::M68k::Exception::CHK);
MoveToStateSpecific(StandardException);
// //
// Scc // Scc
@ -2425,8 +2428,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(TRAP): BeginState(TRAP):
IdleBus(2); IdleBus(2);
instruction_address_.l += 2; // Push the address of the instruction after the trap. instruction_address_.l += 2; // Push the address of the instruction after the trap.
exception_vector_ = (opcode_ & 15) + InstructionSet::M68k::Exception::TrapBase; RaiseException((opcode_ & 15) + InstructionSet::M68k::Exception::TrapBase);
MoveToStateSpecific(StandardException);
BeginState(TRAPV): BeginState(TRAPV):
Prefetch(); Prefetch();
@ -2434,8 +2436,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToStateSpecific(Decode); MoveToStateSpecific(Decode);
} }
instruction_address_.l += 2; // Push the address of the instruction after the trap. instruction_address_.l += 2; // Push the address of the instruction after the trap.
exception_vector_ = InstructionSet::M68k::Exception::TRAPV; RaiseException(InstructionSet::M68k::Exception::TRAPV);
MoveToStateSpecific(StandardException);
#undef TODOState #undef TODOState
@ -2448,6 +2449,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
#undef Push #undef Push
#undef PerformDynamic #undef PerformDynamic
#undef PerformSpecific #undef PerformSpecific
#undef RaiseException
#undef Prefetch #undef Prefetch
#undef ReadProgramWord #undef ReadProgramWord
#undef ReadDataWord #undef ReadDataWord